Module nrf5340_net_pac::dppic_ns::chenclr
source · [−]Expand description
Channel enable clear register
Structs
Field CH0 reader - Channel 0 enable clear register. Writing 0 has no effect.
Field CH0 writer - Channel 0 enable clear register. Writing 0 has no effect.
Field CH1 reader - Channel 1 enable clear register. Writing 0 has no effect.
Field CH1 writer - Channel 1 enable clear register. Writing 0 has no effect.
Field CH2 reader - Channel 2 enable clear register. Writing 0 has no effect.
Field CH2 writer - Channel 2 enable clear register. Writing 0 has no effect.
Field CH3 reader - Channel 3 enable clear register. Writing 0 has no effect.
Field CH3 writer - Channel 3 enable clear register. Writing 0 has no effect.
Field CH4 reader - Channel 4 enable clear register. Writing 0 has no effect.
Field CH4 writer - Channel 4 enable clear register. Writing 0 has no effect.
Field CH5 reader - Channel 5 enable clear register. Writing 0 has no effect.
Field CH5 writer - Channel 5 enable clear register. Writing 0 has no effect.
Field CH6 reader - Channel 6 enable clear register. Writing 0 has no effect.
Field CH6 writer - Channel 6 enable clear register. Writing 0 has no effect.
Field CH7 reader - Channel 7 enable clear register. Writing 0 has no effect.
Field CH7 writer - Channel 7 enable clear register. Writing 0 has no effect.
Field CH8 reader - Channel 8 enable clear register. Writing 0 has no effect.
Field CH8 writer - Channel 8 enable clear register. Writing 0 has no effect.
Field CH9 reader - Channel 9 enable clear register. Writing 0 has no effect.
Field CH9 writer - Channel 9 enable clear register. Writing 0 has no effect.
Field CH10 reader - Channel 10 enable clear register. Writing 0 has no effect.
Field CH10 writer - Channel 10 enable clear register. Writing 0 has no effect.
Field CH11 reader - Channel 11 enable clear register. Writing 0 has no effect.
Field CH11 writer - Channel 11 enable clear register. Writing 0 has no effect.
Field CH12 reader - Channel 12 enable clear register. Writing 0 has no effect.
Field CH12 writer - Channel 12 enable clear register. Writing 0 has no effect.
Field CH13 reader - Channel 13 enable clear register. Writing 0 has no effect.
Field CH13 writer - Channel 13 enable clear register. Writing 0 has no effect.
Field CH14 reader - Channel 14 enable clear register. Writing 0 has no effect.
Field CH14 writer - Channel 14 enable clear register. Writing 0 has no effect.
Field CH15 reader - Channel 15 enable clear register. Writing 0 has no effect.
Field CH15 writer - Channel 15 enable clear register. Writing 0 has no effect.
Channel enable clear register
Register CHENCLR reader
Register CHENCLR writer
Enums
Channel 0 enable clear register. Writing 0 has no effect.
Channel 0 enable clear register. Writing 0 has no effect.
Channel 1 enable clear register. Writing 0 has no effect.
Channel 1 enable clear register. Writing 0 has no effect.
Channel 2 enable clear register. Writing 0 has no effect.
Channel 2 enable clear register. Writing 0 has no effect.
Channel 3 enable clear register. Writing 0 has no effect.
Channel 3 enable clear register. Writing 0 has no effect.
Channel 4 enable clear register. Writing 0 has no effect.
Channel 4 enable clear register. Writing 0 has no effect.
Channel 5 enable clear register. Writing 0 has no effect.
Channel 5 enable clear register. Writing 0 has no effect.
Channel 6 enable clear register. Writing 0 has no effect.
Channel 6 enable clear register. Writing 0 has no effect.
Channel 7 enable clear register. Writing 0 has no effect.
Channel 7 enable clear register. Writing 0 has no effect.
Channel 8 enable clear register. Writing 0 has no effect.
Channel 8 enable clear register. Writing 0 has no effect.
Channel 9 enable clear register. Writing 0 has no effect.
Channel 9 enable clear register. Writing 0 has no effect.
Channel 10 enable clear register. Writing 0 has no effect.
Channel 10 enable clear register. Writing 0 has no effect.
Channel 11 enable clear register. Writing 0 has no effect.
Channel 11 enable clear register. Writing 0 has no effect.
Channel 12 enable clear register. Writing 0 has no effect.
Channel 12 enable clear register. Writing 0 has no effect.
Channel 13 enable clear register. Writing 0 has no effect.
Channel 13 enable clear register. Writing 0 has no effect.
Channel 14 enable clear register. Writing 0 has no effect.
Channel 14 enable clear register. Writing 0 has no effect.
Channel 15 enable clear register. Writing 0 has no effect.
Channel 15 enable clear register. Writing 0 has no effect.