Module nrf52svd::twim0

I2C compatible Two-Wire Master Interface with EasyDMA 0

Modules

address	Address used in the TWI transfer
enable	Enable TWIM
errorsrc	Error source
events_error	TWI error
events_lastrx	Byte boundary, starting to receive the last byte
events_lasttx	Byte boundary, starting to transmit the last byte
events_rxstarted	Receive sequence started
events_stopped	TWI stopped
events_suspended	Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
events_txstarted	Transmit sequence started
frequency	TWI frequency
inten	Enable or disable interrupt
intenclr	Disable interrupt
intenset	Enable interrupt
shorts	Shortcut register
tasks_resume	Resume TWI transaction
tasks_startrx	Start TWI receive sequence
tasks_starttx	Start TWI transmit sequence
tasks_stop	Stop TWI transaction. Must be issued while the TWI master is not suspended.
tasks_suspend	Suspend TWI transaction

Structs

ADDRESS	Address used in the TWI transfer
ENABLE	Enable TWIM
ERRORSRC	Error source
EVENTS_ERROR	TWI error
EVENTS_LASTRX	Byte boundary, starting to receive the last byte
EVENTS_LASTTX	Byte boundary, starting to transmit the last byte
EVENTS_RXSTARTED	Receive sequence started
EVENTS_STOPPED	TWI stopped
EVENTS_SUSPENDED	Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
EVENTS_TXSTARTED	Transmit sequence started
FREQUENCY	TWI frequency
INTEN	Enable or disable interrupt
INTENCLR	Disable interrupt
INTENSET	Enable interrupt
RegisterBlock	Register block
SHORTS	Shortcut register
TASKS_RESUME	Resume TWI transaction
TASKS_STARTRX	Start TWI receive sequence
TASKS_STARTTX	Start TWI transmit sequence
TASKS_STOP	Stop TWI transaction. Must be issued while the TWI master is not suspended.
TASKS_SUSPEND	Suspend TWI transaction