Module nrf52840_pac::uarte0
source · Expand description
UART with EasyDMA 0
Modules
Baud rate. Accuracy depends on the HFCLK source selected.
Configuration of parity and hardware flow control
Enable UART
Error source Note : this register is read / write one to clear.
CTS is activated (set low). Clear To Send.
Receive buffer is filled up
Last TX byte transmitted
Error detected
CTS is deactivated (set high). Not Clear To Send.
Data received in RXD (but potentially not yet transferred to Data RAM)
UART receiver has started
Receiver timeout
Data sent from TXD
UART transmitter has started
Transmitter stopped
Enable or disable interrupt
Disable interrupt
Enable interrupt
Register block
Unspecified
Register block
RXD EasyDMA channel
Shortcut register
Flush RX FIFO into RX buffer
Start UART receiver
Start UART transmitter
Stop UART receiver
Stop UART transmitter
Register block
TXD EasyDMA channel
Structs
Baud rate. Accuracy depends on the HFCLK source selected.
Configuration of parity and hardware flow control
Enable UART
Error source Note : this register is read / write one to clear.
CTS is activated (set low). Clear To Send.
Receive buffer is filled up
Last TX byte transmitted
Error detected
CTS is deactivated (set high). Not Clear To Send.
Data received in RXD (but potentially not yet transferred to Data RAM)
UART receiver has started
Receiver timeout
Data sent from TXD
UART transmitter has started
Transmitter stopped
Enable or disable interrupt
Disable interrupt
Enable interrupt
Register block
Register block
Register block
Shortcut register
Flush RX FIFO into RX buffer
Start UART receiver
Start UART transmitter
Stop UART receiver
Stop UART transmitter
Register block