Module nrf52840_hal::pac::twim0 [−][src]
Expand description
I2C compatible Two-Wire Master Interface with EasyDMA 0
Modules
Address used in the TWI transfer
Enable TWIM
Error source
TWI error
Byte boundary, starting to receive the last byte
Byte boundary, starting to transmit the last byte
Receive sequence started
TWI stopped
Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
Transmit sequence started
TWI frequency. Accuracy depends on the HFCLK source selected.
Enable or disable interrupt
Disable interrupt
Enable interrupt
Register block Unspecified
Register block RXD EasyDMA channel
Shortcut register
Resume TWI transaction
Start TWI receive sequence
Start TWI transmit sequence
Stop TWI transaction. Must be issued while the TWI master is not suspended.
Suspend TWI transaction
Register block TXD EasyDMA channel
Structs
Type Definitions
Address used in the TWI transfer
Enable TWIM
Error source
TWI error
Byte boundary, starting to receive the last byte
Byte boundary, starting to transmit the last byte
Receive sequence started
TWI stopped
Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
Transmit sequence started
TWI frequency. Accuracy depends on the HFCLK source selected.
Enable or disable interrupt
Disable interrupt
Enable interrupt
Shortcut register
Resume TWI transaction
Start TWI receive sequence
Start TWI transmit sequence
Stop TWI transaction. Must be issued while the TWI master is not suspended.
Suspend TWI transaction