Module nrf52832_pac::twis0
source · Expand description
I2C compatible Two-Wire Slave Interface with EasyDMA 0
Modules
Description collection[0]: TWI slave address 0
Configuration register for the address match mechanism
Enable TWIS
Error source
TWI error
Read command received
Receive sequence started
TWI stopped
Transmit sequence started
Write command received
Enable or disable interrupt
Disable interrupt
Enable interrupt
Status register indicating which address had a match
Over-read character. Character sent out in case of an over-read of the transmit buffer.
Register block
Unspecified
Register block
RXD EasyDMA channel
Shortcut register
Prepare the TWI slave to respond to a write command
Prepare the TWI slave to respond to a read command
Resume TWI transaction
Stop TWI transaction
Suspend TWI transaction
Register block
TXD EasyDMA channel
Structs
Description collection[0]: TWI slave address 0
Configuration register for the address match mechanism
Enable TWIS
Error source
TWI error
Read command received
Receive sequence started
TWI stopped
Transmit sequence started
Write command received
Enable or disable interrupt
Disable interrupt
Enable interrupt
Status register indicating which address had a match
Over-read character. Character sent out in case of an over-read of the transmit buffer.
Register block
Register block
Register block
Shortcut register
Prepare the TWI slave to respond to a write command
Prepare the TWI slave to respond to a read command
Resume TWI transaction
Stop TWI transaction
Suspend TWI transaction
Register block