Struct netlistdb::NetlistDB

pub struct NetlistDB {

    pub name: Substr,
    pub num_cells: usize,
    pub num_logic_pins: usize,
    pub num_pins: usize,
    pub num_nets: usize,
    pub cellname2id: HashMap<HierName, usize>,
    pub pinname2id: HashMap<(HierName, Substr, Option<isize>), usize>,
    pub netname2id: HashMap<(HierName, Substr, Option<isize>), usize>,
    pub celltypes: Vec<Substr>,
    pub cellnames: Vec<HierName>,
    pub pinnames: Vec<(HierName, Substr, Option<isize>)>,
    pub pin2cell: Vec<usize>,
    pub pin2net: Vec<usize>,
    pub cell2pin: VecCSR,
    pub net2pin: VecCSR,
    pub pindirect: Vec<Direction>,
    /* private fields */
}

The netlist storage.

The public members are all READ-ONLY outside. Please modify them through the ECO commands that will be available in the future.

Fields

name: Substr

top-level design name.

num_cells: usize

number of cells/nodes/instances in the netlist.

This is always greater than 1, as the 0th cell is always the top-level macro.

num_logic_pins: usize

number of logical pins.

A logical pin is not necessarily a pin. It might be the I/O port of non-leaf modules, or the result of an assign operation.

num_pins: usize

number of pins.

num_nets: usize

number of nets/wires.

cellname2id: HashMap<HierName, usize>

Cell name to index.

The top-level macro is always the 0th cell, which has a special name of empty string. Also, the hierarchical non-leaf cells do NOT reside in here, yet – they are to-be-added in the future. This map only contains leaf cells.

pinname2id: HashMap<(HierName, Substr, Option<isize>), usize>

Pin name tuple (cell hier name, macro pin type, vec idx) to index.

Pin names are always unique without ambiguity. For top-level named port connections, only the port names are created as valid pin names. The I/O definition can be referred in logicpinname2id (private member).

netname2id: HashMap<(HierName, Substr, Option<isize>), usize>

Net name tuple (net hier name, vec idx) to index.

Multiple nets can be mapped to one single index, due to connected nets across hierarchy boundaries.

celltypes: Vec<Substr>

Cell index to macro name.

cellnames: Vec<HierName>

Cell index to name (hierarchical).

This information actually contains the tree structure that might be useful later when we implement verilog writer.

pinnames: Vec<(HierName, Substr, Option<isize>)>

Pin index to cell hier, macro pin name, and pin index.

pin2cell: Vec<usize>

Pin to parent cell.

pin2net: Vec<usize>

Pin to parent net.

cell2pin: VecCSR

Cell CSR.

net2pin: VecCSR

Net CSR.

Caveat: After assigning directions, it is guaranteed that the net root would be the first in net CSR. Before such assignment, the order is not determined.

pindirect: Vec<Direction>

Pin direction.

Implementations

impl NetlistDB

pub fn from_sverilog(
    sverilog_source: ArcStr,
    top: Option<&str>,
    direction_provider: &impl DirectionProvider
) -> Option<NetlistDB>

Build a database from structural verilog source code.

The top module to be built from can be optionally specified through the top parameter.

There should be a way to specify library pin directions – through a trait called direction provider.

Trait Implementations

impl Debug for NetlistDB

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.