[−][src]Module muscab1_pac::sram0mpc
Memory Protection Controller 0
Modules
blk_cfg | Block Configuration |
blk_idx | Index value for accessing block based look up table |
blk_lut | Block based gating Look Up Table |
blk_max | Maximum value of block based index register |
cidr0 | Component ID 0 |
cidr1 | Component ID 1 |
cidr2 | Component ID 2 |
cidr3 | Component ID 3 |
ctrl | MPC Control register |
int_clear | Interrupt clear |
int_en | Interrupt enable |
int_info1 | Interrupt information 1 |
int_info2 | Interrupt information 2 |
int_set | Interrupt set. Debug purpose only |
int_stat | Interrupt state |
pidr0 | Peripheral ID 0 |
pidr1 | Peripheral ID 1 |
pidr2 | Peripheral ID 2 |
pidr3 | Peripheral ID 3 |
pidr4 | Peripheral ID 4 |
pidr5 | Peripheral ID 5 |
pidr6 | Peripheral ID 6 |
pidr7 | Peripheral ID 7 |
Structs
RegisterBlock | Register block |
Type Definitions
BLK_CFG | Block Configuration |
BLK_IDX | Index value for accessing block based look up table |
BLK_LUT | Block based gating Look Up Table |
BLK_MAX | Maximum value of block based index register |
CIDR0 | Component ID 0 |
CIDR1 | Component ID 1 |
CIDR2 | Component ID 2 |
CIDR3 | Component ID 3 |
CTRL | MPC Control register |
INT_CLEAR | Interrupt clear |
INT_EN | Interrupt enable |
INT_INFO1 | Interrupt information 1 |
INT_INFO2 | Interrupt information 2 |
INT_SET | Interrupt set. Debug purpose only |
INT_STAT | Interrupt state |
PIDR0 | Peripheral ID 0 |
PIDR1 | Peripheral ID 1 |
PIDR2 | Peripheral ID 2 |
PIDR3 | Peripheral ID 3 |
PIDR4 | Peripheral ID 4 |
PIDR5 | Peripheral ID 5 |
PIDR6 | Peripheral ID 6 |
PIDR7 | Peripheral ID 7 |