Crate mspm0l130x

Source
Expand description

Peripheral access API for MSPM0L130X microcontrollers (generated using svd2rust v0.30.2 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Modules§

adc0
PERIPHERALREGION
adc0_svt
PERIPHERALREGIONSVT
comp0
PERIPHERALREGION
cpuss
CPUSSMMR
crc
PERIPHERALREGION
debugss
DSSM
dma
PERIPHERALREGION
flashctl
F65NW
generic
Common register and bit access and modify traits
gpioa
PERIPHERALREGION
i2c0
PERIPHERALREGION
i2c1
PERIPHERALREGION
iomux
PERIPHERALREGION
opa0
PERIPHERALREGION
opa1
PERIPHERALREGION
spi0
PERIPHERALREGION
sysctl
mem_map
timg0
PERIPHERALREGION
timg1
PERIPHERALREGION
timg2
PERIPHERALREGION
timg4
PERIPHERALREGION
uart0
PERIPHERALREGION
uart1
PERIPHERALREGION
vref
PERIPHERALREGION
wuc
PERIPHERALREGION
wwdt0
WWDT

Structs§

ADC0
PERIPHERALREGION
ADC0_SVT
PERIPHERALREGIONSVT
CBP
Cache and branch predictor maintenance operations
COMP0
PERIPHERALREGION
CPUID
CPUID
CPUSS
CPUSSMMR
CRC
PERIPHERALREGION
CorePeripherals
Core peripherals
DCB
Debug Control Block
DEBUGSS
DSSM
DMA
PERIPHERALREGION
DWT
Data Watchpoint and Trace unit
FLASHCTL
F65NW
FPB
Flash Patch and Breakpoint unit
GPIOA
PERIPHERALREGION
I2C0
PERIPHERALREGION
I2C1
PERIPHERALREGION
IOMUX
PERIPHERALREGION
ITM
Instrumentation Trace Macrocell
MPU
Memory Protection Unit
NVIC
Nested Vector Interrupt Controller
OPA0
PERIPHERALREGION
OPA1
PERIPHERALREGION
Peripherals
All the peripherals.
SCB
System Control Block
SPI0
PERIPHERALREGION
SYSCTL
mem_map
SYST
SysTick: System Timer
TIMG0
PERIPHERALREGION
TIMG1
PERIPHERALREGION
TIMG2
PERIPHERALREGION
TIMG4
PERIPHERALREGION
TPIU
Trace Port Interface Unit
UART0
PERIPHERALREGION
UART1
PERIPHERALREGION
VREF
PERIPHERALREGION
WUC
PERIPHERALREGION
WWDT0
WWDT

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS
Number available in the NVIC for configuring priority