[−][src]Module msp430fr2355::cs::csctl6
Clock System Control 6
Structs
DIVA_W | Write proxy for field |
XT1AUTOOFF_W | Write proxy for field |
XT1AGCOFF_W | Write proxy for field |
XT1HFFREQ_W | Write proxy for field |
XT1BYPASS_W | Write proxy for field |
XT1DRIVE_W | Write proxy for field |
XT1FAULTOFF_W | Write proxy for field |
XTS_W | Write proxy for field |
Enums
DIVA_A | ACLK source divider. |
XT1AUTOOFF_A | XT1 automatic off enable. This bit allows XT1 turned turns off when it is not used |
XT1AGCOFF_A | Automatic Gain Control (AGC) disable. |
XT1HFFREQ_A | The XT1 High-frequency selection. These bits must be set to appropriate frequency for crystal or bypass modes of operation. |
XT1BYPASS_A | XT1 bypass select |
XT1DRIVE_A | The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. The configuration of these bits is retained during LPM3.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore, reconfiguration after wake-up from LPM3.5 before clearing LOCKLPM5 is required. |
XT1FAULTOFF_A | The XT1 oscillator fault detection off |
XTS_A | XT1 mode select |
Type Definitions
DIVA_R | Reader of field |
R | Reader of register CSCTL6 |
W | Writer for register CSCTL6 |
XT1AUTOOFF_R | Reader of field |
XT1AGCOFF_R | Reader of field |
XT1HFFREQ_R | Reader of field |
XT1BYPASS_R | Reader of field |
XT1DRIVE_R | Reader of field |
XT1FAULTOFF_R | Reader of field |
XTS_R | Reader of field |