Module msp430fr2355::cs::csctl3

Clock System Control 3

Structs

FLLREFDIV_W	Write proxy for field FLLREFDIV
REFOLP_W	Write proxy for field REFOLP
SELREF_W	Write proxy for field SELREF

Enums

FLLREFDIV_A	FLL reference divider. These bits define the divide factor for f(FLLREFCLK). If XT1 supports high frequency input higher than 32 kHz, the divided frequency is used as the FLL reference frequency. If XT1 only supports 32-kHz clock, FLLREFDIV is always read and written as zero, 000b = fFLLREFCLK / 1
REFOLP_A	REFO Low Power Enable. This bit turns on REFO low-power mode. During switch, the low-power mode will be invalid until REFOREADY is set.
SELREF_A	FLL reference select. These bits select the FLL reference clock source.

Type Definitions

FLLREFDIV_R	Reader of field FLLREFDIV
R	Reader of register CSCTL3
REFOLP_R	Reader of field REFOLP
SELREF_R	Reader of field SELREF
W	Writer for register CSCTL3