Module msp430fr2355::cs::csctl2

Clock System Control 2

Structs

FLLD_W	Write proxy for field FLLD
FLLN_W	Write proxy for field FLLN

Enums

FLLD_A	FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits.
FLLN_A	Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1.

Type Definitions

FLLD_R	Reader of field FLLD
FLLN_R	Reader of field FLLN
R	Reader of register CSCTL2
W	Writer for register CSCTL2