Module moore_vhdl::ty2
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The VHDL type system.
This module implements the VHDL type system in a fairly isolated manner. The intention is to decouple the type logic as far as possible from details about other parts of the compiler.
See IEEE 1076-2008 section 5 for all the details.
Structs
An access type.
An array type.
A big signed integer type.
An enumeration base type.
A real base type.
An integer base type.
A null type.
A physical base type.
A unit of a physical type.
A directed range of values.
A subtype of a scalar type.
A subtype declaration.
An arena to allocate types nodes into.
A type declaration.
A type mark.
A universal integer.
A universal real.
Enums
A type.
An enumeration variant.
An owned type.
A range direction.
A type name.
Traits
An enumeration type.
A real type.
An integer type.
A physical type.
An interface for dealing with subtypes.
An interface for dealing with types.
Type Definitions
A subtype of an enumeration type.
A subtype of an real type.
A range of integer values.
A subtype of an integer type.
A subtype of an integer type.
A range of real values.