[−][src]Module moore_svlog::mir
The medium-level intermediate representation for SystemVerilog.
Represents a fully typed SystemVerilog design with all implicit operations converted into explicit nodes.
Modules
lower | Lowering to MIR. |
Structs
Lvalue | An lvalue expression. |
Ref | An MIR node reference |
Rvalue | An rvalue expression. |
Enums
BinaryBitwiseOp | The binary bitwise operators. |
IntBinaryArithOp | The integer binary arithmetic operators. |
IntCompOp | The integer comparison operators. |
IntUnaryArithOp | The integer unary arithmetic operators. |
LvalueKind | The different forms an lvalue expression may take. |
RvalueKind | The different forms an rvalue expression may take. |
ShiftOp | The shift operators. |
UnaryBitwiseOp | The unary bitwise operators. |