This crate implements parsing SystemVerilog source files into an abstract syntax tree and resolving the encountered names.
An abstract syntax tree for SystemVerilog.
The categorizing lexer. Tokenizes an input stream of characters, yielding a stream of newline, whitespace, comment, symbol, and text tokens.
A lexical analyzer for SystemVerilog files, based on IEEE 1800-2009, section 5.
A parser for the SystemVerilog language. Based on IEEE 1800-2009.
A preprocessor for SystemVerilog files that takes the raw stream of tokens generated by a lexer and performs include and macro resolution.
Defines all tokens that may result from performing lexical analysis on a SystemVerilog source file. This module is inspired heavily by the tokens used in the Rust compiler.