Module mkl25z4::sim::clkdiv1

System Clock Divider Register 1

Structs

OUTDIV1_W	Write proxy for field OUTDIV1
OUTDIV4_W	Write proxy for field OUTDIV4

Enums

OUTDIV1_A	Clock 1 output divider value
OUTDIV4_A	Clock 4 output divider value

Type Definitions

OUTDIV1_R	Reader of field OUTDIV1
OUTDIV4_R	Reader of field OUTDIV4
R	Reader of register CLKDIV1
W	Writer for register CLKDIV1