#[doc = "Reader of register SCGC4"]
pub type R = crate::R<u32, super::SCGC4>;
#[doc = "Writer for register SCGC4"]
pub type W = crate::W<u32, super::SCGC4>;
#[doc = "Register SCGC4 `reset()`'s with value 0xf000_0030"]
impl crate::ResetValue for super::SCGC4 {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0xf000_0030
}
}
#[doc = "I2C0 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C0_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<I2C0_A> for bool {
#[inline(always)]
fn from(variant: I2C0_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `I2C0`"]
pub type I2C0_R = crate::R<bool, I2C0_A>;
impl I2C0_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> I2C0_A {
match self.bits {
false => I2C0_A::_0,
true => I2C0_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == I2C0_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == I2C0_A::_1
}
}
#[doc = "Write proxy for field `I2C0`"]
pub struct I2C0_W<'a> {
w: &'a mut W,
}
impl<'a> I2C0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C0_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(I2C0_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(I2C0_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
self.w
}
}
#[doc = "I2C1 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C1_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<I2C1_A> for bool {
#[inline(always)]
fn from(variant: I2C1_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `I2C1`"]
pub type I2C1_R = crate::R<bool, I2C1_A>;
impl I2C1_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> I2C1_A {
match self.bits {
false => I2C1_A::_0,
true => I2C1_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == I2C1_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == I2C1_A::_1
}
}
#[doc = "Write proxy for field `I2C1`"]
pub struct I2C1_W<'a> {
w: &'a mut W,
}
impl<'a> I2C1_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C1_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(I2C1_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(I2C1_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w
}
}
#[doc = "UART0 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UART0_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<UART0_A> for bool {
#[inline(always)]
fn from(variant: UART0_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `UART0`"]
pub type UART0_R = crate::R<bool, UART0_A>;
impl UART0_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> UART0_A {
match self.bits {
false => UART0_A::_0,
true => UART0_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == UART0_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == UART0_A::_1
}
}
#[doc = "Write proxy for field `UART0`"]
pub struct UART0_W<'a> {
w: &'a mut W,
}
impl<'a> UART0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UART0_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(UART0_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(UART0_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
self.w
}
}
#[doc = "UART1 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UART1_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<UART1_A> for bool {
#[inline(always)]
fn from(variant: UART1_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `UART1`"]
pub type UART1_R = crate::R<bool, UART1_A>;
impl UART1_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> UART1_A {
match self.bits {
false => UART1_A::_0,
true => UART1_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == UART1_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == UART1_A::_1
}
}
#[doc = "Write proxy for field `UART1`"]
pub struct UART1_W<'a> {
w: &'a mut W,
}
impl<'a> UART1_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UART1_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(UART1_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(UART1_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
self.w
}
}
#[doc = "UART2 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum UART2_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<UART2_A> for bool {
#[inline(always)]
fn from(variant: UART2_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `UART2`"]
pub type UART2_R = crate::R<bool, UART2_A>;
impl UART2_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> UART2_A {
match self.bits {
false => UART2_A::_0,
true => UART2_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == UART2_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == UART2_A::_1
}
}
#[doc = "Write proxy for field `UART2`"]
pub struct UART2_W<'a> {
w: &'a mut W,
}
impl<'a> UART2_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UART2_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(UART2_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(UART2_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
self.w
}
}
#[doc = "USB Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum USBOTG_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<USBOTG_A> for bool {
#[inline(always)]
fn from(variant: USBOTG_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `USBOTG`"]
pub type USBOTG_R = crate::R<bool, USBOTG_A>;
impl USBOTG_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> USBOTG_A {
match self.bits {
false => USBOTG_A::_0,
true => USBOTG_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == USBOTG_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == USBOTG_A::_1
}
}
#[doc = "Write proxy for field `USBOTG`"]
pub struct USBOTG_W<'a> {
w: &'a mut W,
}
impl<'a> USBOTG_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USBOTG_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(USBOTG_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(USBOTG_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
self.w
}
}
#[doc = "Comparator Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CMP_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<CMP_A> for bool {
#[inline(always)]
fn from(variant: CMP_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `CMP`"]
pub type CMP_R = crate::R<bool, CMP_A>;
impl CMP_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> CMP_A {
match self.bits {
false => CMP_A::_0,
true => CMP_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == CMP_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == CMP_A::_1
}
}
#[doc = "Write proxy for field `CMP`"]
pub struct CMP_W<'a> {
w: &'a mut W,
}
impl<'a> CMP_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CMP_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(CMP_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(CMP_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
self.w
}
}
#[doc = "SPI0 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPI0_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<SPI0_A> for bool {
#[inline(always)]
fn from(variant: SPI0_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `SPI0`"]
pub type SPI0_R = crate::R<bool, SPI0_A>;
impl SPI0_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> SPI0_A {
match self.bits {
false => SPI0_A::_0,
true => SPI0_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == SPI0_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == SPI0_A::_1
}
}
#[doc = "Write proxy for field `SPI0`"]
pub struct SPI0_W<'a> {
w: &'a mut W,
}
impl<'a> SPI0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SPI0_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(SPI0_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(SPI0_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
self.w
}
}
#[doc = "SPI1 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPI1_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<SPI1_A> for bool {
#[inline(always)]
fn from(variant: SPI1_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `SPI1`"]
pub type SPI1_R = crate::R<bool, SPI1_A>;
impl SPI1_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> SPI1_A {
match self.bits {
false => SPI1_A::_0,
true => SPI1_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == SPI1_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == SPI1_A::_1
}
}
#[doc = "Write proxy for field `SPI1`"]
pub struct SPI1_W<'a> {
w: &'a mut W,
}
impl<'a> SPI1_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SPI1_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(SPI1_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(SPI1_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
self.w
}
}
impl R {
#[doc = "Bit 6 - I2C0 Clock Gate Control"]
#[inline(always)]
pub fn i2c0(&self) -> I2C0_R {
I2C0_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 7 - I2C1 Clock Gate Control"]
#[inline(always)]
pub fn i2c1(&self) -> I2C1_R {
I2C1_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bit 10 - UART0 Clock Gate Control"]
#[inline(always)]
pub fn uart0(&self) -> UART0_R {
UART0_R::new(((self.bits >> 10) & 0x01) != 0)
}
#[doc = "Bit 11 - UART1 Clock Gate Control"]
#[inline(always)]
pub fn uart1(&self) -> UART1_R {
UART1_R::new(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bit 12 - UART2 Clock Gate Control"]
#[inline(always)]
pub fn uart2(&self) -> UART2_R {
UART2_R::new(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bit 18 - USB Clock Gate Control"]
#[inline(always)]
pub fn usbotg(&self) -> USBOTG_R {
USBOTG_R::new(((self.bits >> 18) & 0x01) != 0)
}
#[doc = "Bit 19 - Comparator Clock Gate Control"]
#[inline(always)]
pub fn cmp(&self) -> CMP_R {
CMP_R::new(((self.bits >> 19) & 0x01) != 0)
}
#[doc = "Bit 22 - SPI0 Clock Gate Control"]
#[inline(always)]
pub fn spi0(&self) -> SPI0_R {
SPI0_R::new(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bit 23 - SPI1 Clock Gate Control"]
#[inline(always)]
pub fn spi1(&self) -> SPI1_R {
SPI1_R::new(((self.bits >> 23) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 6 - I2C0 Clock Gate Control"]
#[inline(always)]
pub fn i2c0(&mut self) -> I2C0_W {
I2C0_W { w: self }
}
#[doc = "Bit 7 - I2C1 Clock Gate Control"]
#[inline(always)]
pub fn i2c1(&mut self) -> I2C1_W {
I2C1_W { w: self }
}
#[doc = "Bit 10 - UART0 Clock Gate Control"]
#[inline(always)]
pub fn uart0(&mut self) -> UART0_W {
UART0_W { w: self }
}
#[doc = "Bit 11 - UART1 Clock Gate Control"]
#[inline(always)]
pub fn uart1(&mut self) -> UART1_W {
UART1_W { w: self }
}
#[doc = "Bit 12 - UART2 Clock Gate Control"]
#[inline(always)]
pub fn uart2(&mut self) -> UART2_W {
UART2_W { w: self }
}
#[doc = "Bit 18 - USB Clock Gate Control"]
#[inline(always)]
pub fn usbotg(&mut self) -> USBOTG_W {
USBOTG_W { w: self }
}
#[doc = "Bit 19 - Comparator Clock Gate Control"]
#[inline(always)]
pub fn cmp(&mut self) -> CMP_W {
CMP_W { w: self }
}
#[doc = "Bit 22 - SPI0 Clock Gate Control"]
#[inline(always)]
pub fn spi0(&mut self) -> SPI0_W {
SPI0_W { w: self }
}
#[doc = "Bit 23 - SPI1 Clock Gate Control"]
#[inline(always)]
pub fn spi1(&mut self) -> SPI1_W {
SPI1_W { w: self }
}
}