Module mk20d7::dma

source ·
Expand description

Enhanced direct memory access controller

Modules

  • cdne
    Clear DONE Status Bit Register
  • ceei
    Clear Enable Error Interrupt Register
  • cerq
    Clear Enable Request Register
  • cerr
    Clear Error Register
  • cint
    Clear Interrupt Request Register
  • cr
    Control Register
  • dchpri
    Channel n Priority Register
  • eei
    Enable Error Interrupt Register
  • erq
    Enable Request Register
  • err
    Error Register
  • es
    Error Status Register
  • hrs
    Hardware Request Status Register
  • int
    Interrupt Request Register
  • seei
    Set Enable Error Interrupt Register
  • serq
    Set Enable Request Register
  • ssrt
    Set START Bit Register
  • tcd_attr
    TCD Transfer Attributes
  • tcd_biter_elinkno
    TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  • tcd_biter_elinkyes
    TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  • tcd_citer_elinkno
    TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  • tcd_citer_elinkyes
    TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  • tcd_csr
    TCD Control and Status
  • tcd_daddr
    TCD Destination Address
  • tcd_dlastsga
    TCD Last Destination Address Adjustment/Scatter Gather Address
  • tcd_doff
    TCD Signed Destination Address Offset
  • tcd_nbytes_mlno
    TCD Minor Byte Count (Minor Loop Disabled)
  • tcd_nbytes_mloffno
    TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  • tcd_nbytes_mloffyes
    TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  • tcd_saddr
    TCD Source Address
  • tcd_slast
    TCD Last Source Address Adjustment
  • tcd_soff
    TCD Signed Source Address Offset

Structs

  • CDNE
    Clear DONE Status Bit Register
  • CEEI
    Clear Enable Error Interrupt Register
  • CERQ
    Clear Enable Request Register
  • CERR
    Clear Error Register
  • CINT
    Clear Interrupt Request Register
  • CR
    Control Register
  • DCHPRI
    Channel n Priority Register
  • EEI
    Enable Error Interrupt Register
  • ERQ
    Enable Request Register
  • ERR
    Error Register
  • ES
    Error Status Register
  • HRS
    Hardware Request Status Register
  • INT
    Interrupt Request Register
  • RegisterBlock
    Register block
  • SEEI
    Set Enable Error Interrupt Register
  • SERQ
    Set Enable Request Register
  • SSRT
    Set START Bit Register
  • TCD_ATTR
    TCD Transfer Attributes
  • TCD_BITER_ELINKNO
    TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  • TCD_BITER_ELINKYES
    TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  • TCD_CITER_ELINKNO
    TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  • TCD_CITER_ELINKYES
    TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  • TCD_CSR
    TCD Control and Status
  • TCD_DADDR
    TCD Destination Address
  • TCD_DLASTSGA
    TCD Last Destination Address Adjustment/Scatter Gather Address
  • TCD_DOFF
    TCD Signed Destination Address Offset
  • TCD_NBYTES_MLNO
    TCD Minor Byte Count (Minor Loop Disabled)
  • TCD_NBYTES_MLOFFNO
    TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  • TCD_NBYTES_MLOFFYES
    TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  • TCD_SADDR
    TCD Source Address
  • TCD_SLAST
    TCD Last Source Address Adjustment
  • TCD_SOFF
    TCD Signed Source Address Offset