Struct mk20d7::sim::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub sopt1: SOPT1,
    pub sopt1cfg: SOPT1CFG,
    pub sopt2: SOPT2,
    pub sopt4: SOPT4,
    pub sopt5: SOPT5,
    pub sopt7: SOPT7,
    pub sdid: SDID,
    pub scgc1: SCGC1,
    pub scgc2: SCGC2,
    pub scgc3: SCGC3,
    pub scgc4: SCGC4,
    pub scgc5: SCGC5,
    pub scgc6: SCGC6,
    pub scgc7: SCGC7,
    pub clkdiv1: CLKDIV1,
    pub clkdiv2: CLKDIV2,
    pub fcfg1: FCFG1,
    pub fcfg2: FCFG2,
    pub uidh: UIDH,
    pub uidmh: UIDMH,
    pub uidml: UIDML,
    pub uidl: UIDL,
    // some fields omitted
}

Register block

Fields

sopt1: SOPT1

0x00 - System Options Register 1

sopt1cfg: SOPT1CFG

0x04 - SOPT1 Configuration Register

sopt2: SOPT2

0x1004 - System Options Register 2

sopt4: SOPT4

0x100c - System Options Register 4

sopt5: SOPT5

0x1010 - System Options Register 5

sopt7: SOPT7

0x1018 - System Options Register 7

sdid: SDID

0x1024 - System Device Identification Register

scgc1: SCGC1

0x1028 - System Clock Gating Control Register 1

scgc2: SCGC2

0x102c - System Clock Gating Control Register 2

scgc3: SCGC3

0x1030 - System Clock Gating Control Register 3

scgc4: SCGC4

0x1034 - System Clock Gating Control Register 4

scgc5: SCGC5

0x1038 - System Clock Gating Control Register 5

scgc6: SCGC6

0x103c - System Clock Gating Control Register 6

scgc7: SCGC7

0x1040 - System Clock Gating Control Register 7

clkdiv1: CLKDIV1

0x1044 - System Clock Divider Register 1

clkdiv2: CLKDIV2

0x1048 - System Clock Divider Register 2

fcfg1: FCFG1

0x104c - Flash Configuration Register 1

fcfg2: FCFG2

0x1050 - Flash Configuration Register 2

uidh: UIDH

0x1054 - Unique Identification Register High

uidmh: UIDMH

0x1058 - Unique Identification Register Mid-High

uidml: UIDML

0x105c - Unique Identification Register Mid Low

uidl: UIDL

0x1060 - Unique Identification Register Low

Trait Implementations