mimxrt685s_pac/wwdt0/
mod_.rs

1#[doc = "Register `MOD` reader"]
2pub type R = crate::R<ModSpec>;
3#[doc = "Register `MOD` writer"]
4pub type W = crate::W<ModSpec>;
5#[doc = "Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Wden {
9    #[doc = "0: Stop. The watchdog timer is stopped."]
10    Stop = 0,
11    #[doc = "1: Run. The watchdog timer is running."]
12    Run = 1,
13}
14impl From<Wden> for bool {
15    #[inline(always)]
16    fn from(variant: Wden) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `WDEN` reader - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently."]
21pub type WdenR = crate::BitReader<Wden>;
22impl WdenR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Wden {
26        match self.bits {
27            false => Wden::Stop,
28            true => Wden::Run,
29        }
30    }
31    #[doc = "Stop. The watchdog timer is stopped."]
32    #[inline(always)]
33    pub fn is_stop(&self) -> bool {
34        *self == Wden::Stop
35    }
36    #[doc = "Run. The watchdog timer is running."]
37    #[inline(always)]
38    pub fn is_run(&self) -> bool {
39        *self == Wden::Run
40    }
41}
42#[doc = "Field `WDEN` writer - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently."]
43pub type WdenW<'a, REG> = crate::BitWriter<'a, REG, Wden>;
44impl<'a, REG> WdenW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Stop. The watchdog timer is stopped."]
49    #[inline(always)]
50    pub fn stop(self) -> &'a mut crate::W<REG> {
51        self.variant(Wden::Stop)
52    }
53    #[doc = "Run. The watchdog timer is running."]
54    #[inline(always)]
55    pub fn run(self) -> &'a mut crate::W<REG> {
56        self.variant(Wden::Run)
57    }
58}
59#[doc = "Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Wdreset {
63    #[doc = "0: Interrupt. A watchdog time-out will not cause a chip reset."]
64    Interrupt = 0,
65    #[doc = "1: Reset. A watchdog time-out will cause a chip reset."]
66    Reset = 1,
67}
68impl From<Wdreset> for bool {
69    #[inline(always)]
70    fn from(variant: Wdreset) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `WDRESET` reader - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0."]
75pub type WdresetR = crate::BitReader<Wdreset>;
76impl WdresetR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Wdreset {
80        match self.bits {
81            false => Wdreset::Interrupt,
82            true => Wdreset::Reset,
83        }
84    }
85    #[doc = "Interrupt. A watchdog time-out will not cause a chip reset."]
86    #[inline(always)]
87    pub fn is_interrupt(&self) -> bool {
88        *self == Wdreset::Interrupt
89    }
90    #[doc = "Reset. A watchdog time-out will cause a chip reset."]
91    #[inline(always)]
92    pub fn is_reset(&self) -> bool {
93        *self == Wdreset::Reset
94    }
95}
96#[doc = "Field `WDRESET` writer - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0."]
97pub type WdresetW<'a, REG> = crate::BitWriter<'a, REG, Wdreset>;
98impl<'a, REG> WdresetW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Interrupt. A watchdog time-out will not cause a chip reset."]
103    #[inline(always)]
104    pub fn interrupt(self) -> &'a mut crate::W<REG> {
105        self.variant(Wdreset::Interrupt)
106    }
107    #[doc = "Reset. A watchdog time-out will cause a chip reset."]
108    #[inline(always)]
109    pub fn reset(self) -> &'a mut crate::W<REG> {
110        self.variant(Wdreset::Reset)
111    }
112}
113#[doc = "Field `WDTOF` reader - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1."]
114pub type WdtofR = crate::BitReader;
115#[doc = "Field `WDTOF` writer - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1."]
116pub type WdtofW<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `WDINT` reader - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0."]
118pub type WdintR = crate::BitReader;
119#[doc = "Field `WDINT` writer - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0."]
120pub type WdintW<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Watchdog update mode. This bit can be set once by software and is only cleared by a reset.\n\nValue on reset: 0"]
122#[cfg_attr(feature = "defmt", derive(defmt::Format))]
123#[derive(Clone, Copy, Debug, PartialEq, Eq)]
124pub enum Wdprotect {
125    #[doc = "0: Flexible. The watchdog time-out value (TC) can be changed at any time."]
126    Flexible = 0,
127    #[doc = "1: Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW."]
128    Threshold = 1,
129}
130impl From<Wdprotect> for bool {
131    #[inline(always)]
132    fn from(variant: Wdprotect) -> Self {
133        variant as u8 != 0
134    }
135}
136#[doc = "Field `WDPROTECT` reader - Watchdog update mode. This bit can be set once by software and is only cleared by a reset."]
137pub type WdprotectR = crate::BitReader<Wdprotect>;
138impl WdprotectR {
139    #[doc = "Get enumerated values variant"]
140    #[inline(always)]
141    pub const fn variant(&self) -> Wdprotect {
142        match self.bits {
143            false => Wdprotect::Flexible,
144            true => Wdprotect::Threshold,
145        }
146    }
147    #[doc = "Flexible. The watchdog time-out value (TC) can be changed at any time."]
148    #[inline(always)]
149    pub fn is_flexible(&self) -> bool {
150        *self == Wdprotect::Flexible
151    }
152    #[doc = "Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW."]
153    #[inline(always)]
154    pub fn is_threshold(&self) -> bool {
155        *self == Wdprotect::Threshold
156    }
157}
158#[doc = "Field `WDPROTECT` writer - Watchdog update mode. This bit can be set once by software and is only cleared by a reset."]
159pub type WdprotectW<'a, REG> = crate::BitWriter<'a, REG, Wdprotect>;
160impl<'a, REG> WdprotectW<'a, REG>
161where
162    REG: crate::Writable + crate::RegisterSpec,
163{
164    #[doc = "Flexible. The watchdog time-out value (TC) can be changed at any time."]
165    #[inline(always)]
166    pub fn flexible(self) -> &'a mut crate::W<REG> {
167        self.variant(Wdprotect::Flexible)
168    }
169    #[doc = "Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW."]
170    #[inline(always)]
171    pub fn threshold(self) -> &'a mut crate::W<REG> {
172        self.variant(Wdprotect::Threshold)
173    }
174}
175#[doc = "Field `LOCK` reader - Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset."]
176pub type LockR = crate::BitReader;
177#[doc = "Field `LOCK` writer - Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset."]
178pub type LockW<'a, REG> = crate::BitWriter<'a, REG>;
179impl R {
180    #[doc = "Bit 0 - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently."]
181    #[inline(always)]
182    pub fn wden(&self) -> WdenR {
183        WdenR::new((self.bits & 1) != 0)
184    }
185    #[doc = "Bit 1 - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0."]
186    #[inline(always)]
187    pub fn wdreset(&self) -> WdresetR {
188        WdresetR::new(((self.bits >> 1) & 1) != 0)
189    }
190    #[doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1."]
191    #[inline(always)]
192    pub fn wdtof(&self) -> WdtofR {
193        WdtofR::new(((self.bits >> 2) & 1) != 0)
194    }
195    #[doc = "Bit 3 - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0."]
196    #[inline(always)]
197    pub fn wdint(&self) -> WdintR {
198        WdintR::new(((self.bits >> 3) & 1) != 0)
199    }
200    #[doc = "Bit 4 - Watchdog update mode. This bit can be set once by software and is only cleared by a reset."]
201    #[inline(always)]
202    pub fn wdprotect(&self) -> WdprotectR {
203        WdprotectR::new(((self.bits >> 4) & 1) != 0)
204    }
205    #[doc = "Bit 5 - Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset."]
206    #[inline(always)]
207    pub fn lock(&self) -> LockR {
208        LockR::new(((self.bits >> 5) & 1) != 0)
209    }
210}
211#[cfg(feature = "debug")]
212impl core::fmt::Debug for R {
213    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
214        f.debug_struct("MOD")
215            .field("wden", &self.wden())
216            .field("wdreset", &self.wdreset())
217            .field("wdtof", &self.wdtof())
218            .field("wdint", &self.wdint())
219            .field("wdprotect", &self.wdprotect())
220            .field("lock", &self.lock())
221            .finish()
222    }
223}
224impl W {
225    #[doc = "Bit 0 - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently."]
226    #[inline(always)]
227    pub fn wden(&mut self) -> WdenW<ModSpec> {
228        WdenW::new(self, 0)
229    }
230    #[doc = "Bit 1 - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0."]
231    #[inline(always)]
232    pub fn wdreset(&mut self) -> WdresetW<ModSpec> {
233        WdresetW::new(self, 1)
234    }
235    #[doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a chip reset if WDRESET = 1."]
236    #[inline(always)]
237    pub fn wdtof(&mut self) -> WdtofW<ModSpec> {
238        WdtofW::new(self, 2)
239    }
240    #[doc = "Bit 3 - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the WARNINT value is equal to the value of the TV register. This can occur if the value of WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0."]
241    #[inline(always)]
242    pub fn wdint(&mut self) -> WdintW<ModSpec> {
243        WdintW::new(self, 3)
244    }
245    #[doc = "Bit 4 - Watchdog update mode. This bit can be set once by software and is only cleared by a reset."]
246    #[inline(always)]
247    pub fn wdprotect(&mut self) -> WdprotectW<ModSpec> {
248        WdprotectW::new(self, 4)
249    }
250    #[doc = "Bit 5 - Once this bit is set to one and a watchdog feed is performed, disabling or powering down the watchdog oscillator is prevented by hardware. This bit can be set once by software and is only cleared by any reset."]
251    #[inline(always)]
252    pub fn lock(&mut self) -> LockW<ModSpec> {
253        LockW::new(self, 5)
254    }
255}
256#[doc = "Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.\n\nYou can [`read`](crate::Reg::read) this register and get [`mod_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mod_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
257pub struct ModSpec;
258impl crate::RegisterSpec for ModSpec {
259    type Ux = u32;
260}
261#[doc = "`read()` method returns [`mod_::R`](R) reader structure"]
262impl crate::Readable for ModSpec {}
263#[doc = "`write(|w| ..)` method takes [`mod_::W`](W) writer structure"]
264impl crate::Writable for ModSpec {
265    type Safety = crate::Unsafe;
266    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
267    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
268}
269#[doc = "`reset()` method sets MOD to value 0"]
270impl crate::Resettable for ModSpec {
271    const RESET_VALUE: u32 = 0;
272}
mimxrt685s_pac/wwdt0/mod_.rs

mimxrt685s_pac/wwdt0/
mod_.rs
