1#[doc = "Register `PRES_STATE` reader"]
2pub type R = crate::R<PresStateSpec>;
3#[doc = "Command Inhibit (CMD)\n\nValue on reset: 0"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Cihb {
7 #[doc = "0: Can issue command using only CMD line"]
8 Cihb0 = 0,
9 #[doc = "1: Cannot issue command"]
10 Cihb1 = 1,
11}
12impl From<Cihb> for bool {
13 #[inline(always)]
14 fn from(variant: Cihb) -> Self {
15 variant as u8 != 0
16 }
17}
18#[doc = "Field `CIHB` reader - Command Inhibit (CMD)"]
19pub type CihbR = crate::BitReader<Cihb>;
20impl CihbR {
21 #[doc = "Get enumerated values variant"]
22 #[inline(always)]
23 pub const fn variant(&self) -> Cihb {
24 match self.bits {
25 false => Cihb::Cihb0,
26 true => Cihb::Cihb1,
27 }
28 }
29 #[doc = "Can issue command using only CMD line"]
30 #[inline(always)]
31 pub fn is_cihb_0(&self) -> bool {
32 *self == Cihb::Cihb0
33 }
34 #[doc = "Cannot issue command"]
35 #[inline(always)]
36 pub fn is_cihb_1(&self) -> bool {
37 *self == Cihb::Cihb1
38 }
39}
40#[doc = "Command Inhibit (DATA)\n\nValue on reset: 0"]
41#[cfg_attr(feature = "defmt", derive(defmt::Format))]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum Cdihb {
44 #[doc = "0: Can issue command which uses the DATA line"]
45 Cdihb0 = 0,
46 #[doc = "1: Cannot issue command which uses the DATA line"]
47 Cdihb1 = 1,
48}
49impl From<Cdihb> for bool {
50 #[inline(always)]
51 fn from(variant: Cdihb) -> Self {
52 variant as u8 != 0
53 }
54}
55#[doc = "Field `CDIHB` reader - Command Inhibit (DATA)"]
56pub type CdihbR = crate::BitReader<Cdihb>;
57impl CdihbR {
58 #[doc = "Get enumerated values variant"]
59 #[inline(always)]
60 pub const fn variant(&self) -> Cdihb {
61 match self.bits {
62 false => Cdihb::Cdihb0,
63 true => Cdihb::Cdihb1,
64 }
65 }
66 #[doc = "Can issue command which uses the DATA line"]
67 #[inline(always)]
68 pub fn is_cdihb_0(&self) -> bool {
69 *self == Cdihb::Cdihb0
70 }
71 #[doc = "Cannot issue command which uses the DATA line"]
72 #[inline(always)]
73 pub fn is_cdihb_1(&self) -> bool {
74 *self == Cdihb::Cdihb1
75 }
76}
77#[doc = "Data Line Active\n\nValue on reset: 0"]
78#[cfg_attr(feature = "defmt", derive(defmt::Format))]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum Dla {
81 #[doc = "0: DATA Line Inactive"]
82 Dla0 = 0,
83 #[doc = "1: DATA Line Active"]
84 Dla1 = 1,
85}
86impl From<Dla> for bool {
87 #[inline(always)]
88 fn from(variant: Dla) -> Self {
89 variant as u8 != 0
90 }
91}
92#[doc = "Field `DLA` reader - Data Line Active"]
93pub type DlaR = crate::BitReader<Dla>;
94impl DlaR {
95 #[doc = "Get enumerated values variant"]
96 #[inline(always)]
97 pub const fn variant(&self) -> Dla {
98 match self.bits {
99 false => Dla::Dla0,
100 true => Dla::Dla1,
101 }
102 }
103 #[doc = "DATA Line Inactive"]
104 #[inline(always)]
105 pub fn is_dla_0(&self) -> bool {
106 *self == Dla::Dla0
107 }
108 #[doc = "DATA Line Active"]
109 #[inline(always)]
110 pub fn is_dla_1(&self) -> bool {
111 *self == Dla::Dla1
112 }
113}
114#[doc = "SD Clock Stable\n\nValue on reset: 0"]
115#[cfg_attr(feature = "defmt", derive(defmt::Format))]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117pub enum Sdstb {
118 #[doc = "0: Clock is changing frequency and not stable."]
119 Sdstb0 = 0,
120 #[doc = "1: Clock is stable."]
121 Sdstb1 = 1,
122}
123impl From<Sdstb> for bool {
124 #[inline(always)]
125 fn from(variant: Sdstb) -> Self {
126 variant as u8 != 0
127 }
128}
129#[doc = "Field `SDSTB` reader - SD Clock Stable"]
130pub type SdstbR = crate::BitReader<Sdstb>;
131impl SdstbR {
132 #[doc = "Get enumerated values variant"]
133 #[inline(always)]
134 pub const fn variant(&self) -> Sdstb {
135 match self.bits {
136 false => Sdstb::Sdstb0,
137 true => Sdstb::Sdstb1,
138 }
139 }
140 #[doc = "Clock is changing frequency and not stable."]
141 #[inline(always)]
142 pub fn is_sdstb_0(&self) -> bool {
143 *self == Sdstb::Sdstb0
144 }
145 #[doc = "Clock is stable."]
146 #[inline(always)]
147 pub fn is_sdstb_1(&self) -> bool {
148 *self == Sdstb::Sdstb1
149 }
150}
151#[doc = "IPG_CLK Gated Off Internally\n\nValue on reset: 0"]
152#[cfg_attr(feature = "defmt", derive(defmt::Format))]
153#[derive(Clone, Copy, Debug, PartialEq, Eq)]
154pub enum Ipgoff {
155 #[doc = "0: IPG_CLK is active."]
156 Ipgoff0 = 0,
157 #[doc = "1: IPG_CLK is gated off."]
158 Ipgoff1 = 1,
159}
160impl From<Ipgoff> for bool {
161 #[inline(always)]
162 fn from(variant: Ipgoff) -> Self {
163 variant as u8 != 0
164 }
165}
166#[doc = "Field `IPGOFF` reader - IPG_CLK Gated Off Internally"]
167pub type IpgoffR = crate::BitReader<Ipgoff>;
168impl IpgoffR {
169 #[doc = "Get enumerated values variant"]
170 #[inline(always)]
171 pub const fn variant(&self) -> Ipgoff {
172 match self.bits {
173 false => Ipgoff::Ipgoff0,
174 true => Ipgoff::Ipgoff1,
175 }
176 }
177 #[doc = "IPG_CLK is active."]
178 #[inline(always)]
179 pub fn is_ipgoff_0(&self) -> bool {
180 *self == Ipgoff::Ipgoff0
181 }
182 #[doc = "IPG_CLK is gated off."]
183 #[inline(always)]
184 pub fn is_ipgoff_1(&self) -> bool {
185 *self == Ipgoff::Ipgoff1
186 }
187}
188#[doc = "HCLK Gated Off Internally\n\nValue on reset: 0"]
189#[cfg_attr(feature = "defmt", derive(defmt::Format))]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum Hckoff {
192 #[doc = "0: HCLK is active."]
193 Hckoff0 = 0,
194 #[doc = "1: HCLK is gated off."]
195 Hckoff1 = 1,
196}
197impl From<Hckoff> for bool {
198 #[inline(always)]
199 fn from(variant: Hckoff) -> Self {
200 variant as u8 != 0
201 }
202}
203#[doc = "Field `HCKOFF` reader - HCLK Gated Off Internally"]
204pub type HckoffR = crate::BitReader<Hckoff>;
205impl HckoffR {
206 #[doc = "Get enumerated values variant"]
207 #[inline(always)]
208 pub const fn variant(&self) -> Hckoff {
209 match self.bits {
210 false => Hckoff::Hckoff0,
211 true => Hckoff::Hckoff1,
212 }
213 }
214 #[doc = "HCLK is active."]
215 #[inline(always)]
216 pub fn is_hckoff_0(&self) -> bool {
217 *self == Hckoff::Hckoff0
218 }
219 #[doc = "HCLK is gated off."]
220 #[inline(always)]
221 pub fn is_hckoff_1(&self) -> bool {
222 *self == Hckoff::Hckoff1
223 }
224}
225#[doc = "IPG_PERCLK Gated Off Internally\n\nValue on reset: 0"]
226#[cfg_attr(feature = "defmt", derive(defmt::Format))]
227#[derive(Clone, Copy, Debug, PartialEq, Eq)]
228pub enum Peroff {
229 #[doc = "0: IPG_PERCLK is active."]
230 Peroff0 = 0,
231 #[doc = "1: IPG_PERCLK is gated off."]
232 Peroff1 = 1,
233}
234impl From<Peroff> for bool {
235 #[inline(always)]
236 fn from(variant: Peroff) -> Self {
237 variant as u8 != 0
238 }
239}
240#[doc = "Field `PEROFF` reader - IPG_PERCLK Gated Off Internally"]
241pub type PeroffR = crate::BitReader<Peroff>;
242impl PeroffR {
243 #[doc = "Get enumerated values variant"]
244 #[inline(always)]
245 pub const fn variant(&self) -> Peroff {
246 match self.bits {
247 false => Peroff::Peroff0,
248 true => Peroff::Peroff1,
249 }
250 }
251 #[doc = "IPG_PERCLK is active."]
252 #[inline(always)]
253 pub fn is_peroff_0(&self) -> bool {
254 *self == Peroff::Peroff0
255 }
256 #[doc = "IPG_PERCLK is gated off."]
257 #[inline(always)]
258 pub fn is_peroff_1(&self) -> bool {
259 *self == Peroff::Peroff1
260 }
261}
262#[doc = "SD Clock Gated Off Internally\n\nValue on reset: 1"]
263#[cfg_attr(feature = "defmt", derive(defmt::Format))]
264#[derive(Clone, Copy, Debug, PartialEq, Eq)]
265pub enum Sdoff {
266 #[doc = "0: SD Clock is active."]
267 Sdoff0 = 0,
268 #[doc = "1: SD Clock is gated off."]
269 Sdoff1 = 1,
270}
271impl From<Sdoff> for bool {
272 #[inline(always)]
273 fn from(variant: Sdoff) -> Self {
274 variant as u8 != 0
275 }
276}
277#[doc = "Field `SDOFF` reader - SD Clock Gated Off Internally"]
278pub type SdoffR = crate::BitReader<Sdoff>;
279impl SdoffR {
280 #[doc = "Get enumerated values variant"]
281 #[inline(always)]
282 pub const fn variant(&self) -> Sdoff {
283 match self.bits {
284 false => Sdoff::Sdoff0,
285 true => Sdoff::Sdoff1,
286 }
287 }
288 #[doc = "SD Clock is active."]
289 #[inline(always)]
290 pub fn is_sdoff_0(&self) -> bool {
291 *self == Sdoff::Sdoff0
292 }
293 #[doc = "SD Clock is gated off."]
294 #[inline(always)]
295 pub fn is_sdoff_1(&self) -> bool {
296 *self == Sdoff::Sdoff1
297 }
298}
299#[doc = "Write Transfer Active\n\nValue on reset: 0"]
300#[cfg_attr(feature = "defmt", derive(defmt::Format))]
301#[derive(Clone, Copy, Debug, PartialEq, Eq)]
302pub enum Wta {
303 #[doc = "0: No valid data"]
304 Wta0 = 0,
305 #[doc = "1: Transferring data"]
306 Wta1 = 1,
307}
308impl From<Wta> for bool {
309 #[inline(always)]
310 fn from(variant: Wta) -> Self {
311 variant as u8 != 0
312 }
313}
314#[doc = "Field `WTA` reader - Write Transfer Active"]
315pub type WtaR = crate::BitReader<Wta>;
316impl WtaR {
317 #[doc = "Get enumerated values variant"]
318 #[inline(always)]
319 pub const fn variant(&self) -> Wta {
320 match self.bits {
321 false => Wta::Wta0,
322 true => Wta::Wta1,
323 }
324 }
325 #[doc = "No valid data"]
326 #[inline(always)]
327 pub fn is_wta_0(&self) -> bool {
328 *self == Wta::Wta0
329 }
330 #[doc = "Transferring data"]
331 #[inline(always)]
332 pub fn is_wta_1(&self) -> bool {
333 *self == Wta::Wta1
334 }
335}
336#[doc = "Read Transfer Active\n\nValue on reset: 0"]
337#[cfg_attr(feature = "defmt", derive(defmt::Format))]
338#[derive(Clone, Copy, Debug, PartialEq, Eq)]
339pub enum Rta {
340 #[doc = "0: No valid data"]
341 Rta0 = 0,
342 #[doc = "1: Transferring data"]
343 Rta1 = 1,
344}
345impl From<Rta> for bool {
346 #[inline(always)]
347 fn from(variant: Rta) -> Self {
348 variant as u8 != 0
349 }
350}
351#[doc = "Field `RTA` reader - Read Transfer Active"]
352pub type RtaR = crate::BitReader<Rta>;
353impl RtaR {
354 #[doc = "Get enumerated values variant"]
355 #[inline(always)]
356 pub const fn variant(&self) -> Rta {
357 match self.bits {
358 false => Rta::Rta0,
359 true => Rta::Rta1,
360 }
361 }
362 #[doc = "No valid data"]
363 #[inline(always)]
364 pub fn is_rta_0(&self) -> bool {
365 *self == Rta::Rta0
366 }
367 #[doc = "Transferring data"]
368 #[inline(always)]
369 pub fn is_rta_1(&self) -> bool {
370 *self == Rta::Rta1
371 }
372}
373#[doc = "Buffer Write Enable\n\nValue on reset: 0"]
374#[cfg_attr(feature = "defmt", derive(defmt::Format))]
375#[derive(Clone, Copy, Debug, PartialEq, Eq)]
376pub enum Bwen {
377 #[doc = "0: Write disable"]
378 Bwen0 = 0,
379 #[doc = "1: Write enable"]
380 Bwen1 = 1,
381}
382impl From<Bwen> for bool {
383 #[inline(always)]
384 fn from(variant: Bwen) -> Self {
385 variant as u8 != 0
386 }
387}
388#[doc = "Field `BWEN` reader - Buffer Write Enable"]
389pub type BwenR = crate::BitReader<Bwen>;
390impl BwenR {
391 #[doc = "Get enumerated values variant"]
392 #[inline(always)]
393 pub const fn variant(&self) -> Bwen {
394 match self.bits {
395 false => Bwen::Bwen0,
396 true => Bwen::Bwen1,
397 }
398 }
399 #[doc = "Write disable"]
400 #[inline(always)]
401 pub fn is_bwen_0(&self) -> bool {
402 *self == Bwen::Bwen0
403 }
404 #[doc = "Write enable"]
405 #[inline(always)]
406 pub fn is_bwen_1(&self) -> bool {
407 *self == Bwen::Bwen1
408 }
409}
410#[doc = "Buffer Read Enable\n\nValue on reset: 0"]
411#[cfg_attr(feature = "defmt", derive(defmt::Format))]
412#[derive(Clone, Copy, Debug, PartialEq, Eq)]
413pub enum Bren {
414 #[doc = "0: Read disable"]
415 Bren0 = 0,
416 #[doc = "1: Read enable"]
417 Bren1 = 1,
418}
419impl From<Bren> for bool {
420 #[inline(always)]
421 fn from(variant: Bren) -> Self {
422 variant as u8 != 0
423 }
424}
425#[doc = "Field `BREN` reader - Buffer Read Enable"]
426pub type BrenR = crate::BitReader<Bren>;
427impl BrenR {
428 #[doc = "Get enumerated values variant"]
429 #[inline(always)]
430 pub const fn variant(&self) -> Bren {
431 match self.bits {
432 false => Bren::Bren0,
433 true => Bren::Bren1,
434 }
435 }
436 #[doc = "Read disable"]
437 #[inline(always)]
438 pub fn is_bren_0(&self) -> bool {
439 *self == Bren::Bren0
440 }
441 #[doc = "Read enable"]
442 #[inline(always)]
443 pub fn is_bren_1(&self) -> bool {
444 *self == Bren::Bren1
445 }
446}
447#[doc = "Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)\n\nValue on reset: 0"]
448#[cfg_attr(feature = "defmt", derive(defmt::Format))]
449#[derive(Clone, Copy, Debug, PartialEq, Eq)]
450pub enum Rtr {
451 #[doc = "0: Fixed or well tuned sampling clock"]
452 Rtr0 = 0,
453 #[doc = "1: Sampling clock needs re-tuning"]
454 Rtr1 = 1,
455}
456impl From<Rtr> for bool {
457 #[inline(always)]
458 fn from(variant: Rtr) -> Self {
459 variant as u8 != 0
460 }
461}
462#[doc = "Field `RTR` reader - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)"]
463pub type RtrR = crate::BitReader<Rtr>;
464impl RtrR {
465 #[doc = "Get enumerated values variant"]
466 #[inline(always)]
467 pub const fn variant(&self) -> Rtr {
468 match self.bits {
469 false => Rtr::Rtr0,
470 true => Rtr::Rtr1,
471 }
472 }
473 #[doc = "Fixed or well tuned sampling clock"]
474 #[inline(always)]
475 pub fn is_rtr_0(&self) -> bool {
476 *self == Rtr::Rtr0
477 }
478 #[doc = "Sampling clock needs re-tuning"]
479 #[inline(always)]
480 pub fn is_rtr_1(&self) -> bool {
481 *self == Rtr::Rtr1
482 }
483}
484#[doc = "Tape Select Change Done\n\nValue on reset: 1"]
485#[cfg_attr(feature = "defmt", derive(defmt::Format))]
486#[derive(Clone, Copy, Debug, PartialEq, Eq)]
487pub enum Tscd {
488 #[doc = "0: Delay cell select change is not finished."]
489 Tscd0 = 0,
490 #[doc = "1: Delay cell select change is finished."]
491 Tscd1 = 1,
492}
493impl From<Tscd> for bool {
494 #[inline(always)]
495 fn from(variant: Tscd) -> Self {
496 variant as u8 != 0
497 }
498}
499#[doc = "Field `TSCD` reader - Tape Select Change Done"]
500pub type TscdR = crate::BitReader<Tscd>;
501impl TscdR {
502 #[doc = "Get enumerated values variant"]
503 #[inline(always)]
504 pub const fn variant(&self) -> Tscd {
505 match self.bits {
506 false => Tscd::Tscd0,
507 true => Tscd::Tscd1,
508 }
509 }
510 #[doc = "Delay cell select change is not finished."]
511 #[inline(always)]
512 pub fn is_tscd_0(&self) -> bool {
513 *self == Tscd::Tscd0
514 }
515 #[doc = "Delay cell select change is finished."]
516 #[inline(always)]
517 pub fn is_tscd_1(&self) -> bool {
518 *self == Tscd::Tscd1
519 }
520}
521#[doc = "Card Inserted\n\nValue on reset: 0"]
522#[cfg_attr(feature = "defmt", derive(defmt::Format))]
523#[derive(Clone, Copy, Debug, PartialEq, Eq)]
524pub enum Cinst {
525 #[doc = "0: Power on Reset or No Card"]
526 Cinst0 = 0,
527 #[doc = "1: Card Inserted"]
528 Cinst1 = 1,
529}
530impl From<Cinst> for bool {
531 #[inline(always)]
532 fn from(variant: Cinst) -> Self {
533 variant as u8 != 0
534 }
535}
536#[doc = "Field `CINST` reader - Card Inserted"]
537pub type CinstR = crate::BitReader<Cinst>;
538impl CinstR {
539 #[doc = "Get enumerated values variant"]
540 #[inline(always)]
541 pub const fn variant(&self) -> Cinst {
542 match self.bits {
543 false => Cinst::Cinst0,
544 true => Cinst::Cinst1,
545 }
546 }
547 #[doc = "Power on Reset or No Card"]
548 #[inline(always)]
549 pub fn is_cinst_0(&self) -> bool {
550 *self == Cinst::Cinst0
551 }
552 #[doc = "Card Inserted"]
553 #[inline(always)]
554 pub fn is_cinst_1(&self) -> bool {
555 *self == Cinst::Cinst1
556 }
557}
558#[doc = "Card Detect Pin Level\n\nValue on reset: 0"]
559#[cfg_attr(feature = "defmt", derive(defmt::Format))]
560#[derive(Clone, Copy, Debug, PartialEq, Eq)]
561pub enum Cdpl {
562 #[doc = "0: No card present (CD_B = 1)"]
563 Cdpl0 = 0,
564 #[doc = "1: Card present (CD_B = 0)"]
565 Cdpl1 = 1,
566}
567impl From<Cdpl> for bool {
568 #[inline(always)]
569 fn from(variant: Cdpl) -> Self {
570 variant as u8 != 0
571 }
572}
573#[doc = "Field `CDPL` reader - Card Detect Pin Level"]
574pub type CdplR = crate::BitReader<Cdpl>;
575impl CdplR {
576 #[doc = "Get enumerated values variant"]
577 #[inline(always)]
578 pub const fn variant(&self) -> Cdpl {
579 match self.bits {
580 false => Cdpl::Cdpl0,
581 true => Cdpl::Cdpl1,
582 }
583 }
584 #[doc = "No card present (CD_B = 1)"]
585 #[inline(always)]
586 pub fn is_cdpl_0(&self) -> bool {
587 *self == Cdpl::Cdpl0
588 }
589 #[doc = "Card present (CD_B = 0)"]
590 #[inline(always)]
591 pub fn is_cdpl_1(&self) -> bool {
592 *self == Cdpl::Cdpl1
593 }
594}
595#[doc = "Write Protect Switch Pin Level\n\nValue on reset: 0"]
596#[cfg_attr(feature = "defmt", derive(defmt::Format))]
597#[derive(Clone, Copy, Debug, PartialEq, Eq)]
598pub enum Wpspl {
599 #[doc = "0: Write protected (WP = 1)"]
600 Wpspl0 = 0,
601 #[doc = "1: Write enabled (WP = 0)"]
602 Wpspl1 = 1,
603}
604impl From<Wpspl> for bool {
605 #[inline(always)]
606 fn from(variant: Wpspl) -> Self {
607 variant as u8 != 0
608 }
609}
610#[doc = "Field `WPSPL` reader - Write Protect Switch Pin Level"]
611pub type WpsplR = crate::BitReader<Wpspl>;
612impl WpsplR {
613 #[doc = "Get enumerated values variant"]
614 #[inline(always)]
615 pub const fn variant(&self) -> Wpspl {
616 match self.bits {
617 false => Wpspl::Wpspl0,
618 true => Wpspl::Wpspl1,
619 }
620 }
621 #[doc = "Write protected (WP = 1)"]
622 #[inline(always)]
623 pub fn is_wpspl_0(&self) -> bool {
624 *self == Wpspl::Wpspl0
625 }
626 #[doc = "Write enabled (WP = 0)"]
627 #[inline(always)]
628 pub fn is_wpspl_1(&self) -> bool {
629 *self == Wpspl::Wpspl1
630 }
631}
632#[doc = "Field `CLSL` reader - CMD Line Signal Level"]
633pub type ClslR = crate::BitReader;
634#[doc = "DATA\\[7:0\\]
635Line Signal Level\n\nValue on reset: 0"]
636#[cfg_attr(feature = "defmt", derive(defmt::Format))]
637#[derive(Clone, Copy, Debug, PartialEq, Eq)]
638#[repr(u8)]
639pub enum Dlsl {
640 #[doc = "0: Data 0 line signal level"]
641 Data0 = 0,
642 #[doc = "1: Data 1 line signal level"]
643 Data1 = 1,
644 #[doc = "2: Data 2 line signal level"]
645 Data2 = 2,
646 #[doc = "3: Data 3 line signal level"]
647 Data3 = 3,
648 #[doc = "4: Data 4 line signal level"]
649 Data4 = 4,
650 #[doc = "5: Data 5 line signal level"]
651 Data5 = 5,
652 #[doc = "6: Data 6 line signal level"]
653 Data6 = 6,
654 #[doc = "7: Data 7 line signal level"]
655 Data7 = 7,
656}
657impl From<Dlsl> for u8 {
658 #[inline(always)]
659 fn from(variant: Dlsl) -> Self {
660 variant as _
661 }
662}
663impl crate::FieldSpec for Dlsl {
664 type Ux = u8;
665}
666impl crate::IsEnum for Dlsl {}
667#[doc = "Field `DLSL` reader - DATA\\[7:0\\]
668Line Signal Level"]
669pub type DlslR = crate::FieldReader<Dlsl>;
670impl DlslR {
671 #[doc = "Get enumerated values variant"]
672 #[inline(always)]
673 pub const fn variant(&self) -> Option<Dlsl> {
674 match self.bits {
675 0 => Some(Dlsl::Data0),
676 1 => Some(Dlsl::Data1),
677 2 => Some(Dlsl::Data2),
678 3 => Some(Dlsl::Data3),
679 4 => Some(Dlsl::Data4),
680 5 => Some(Dlsl::Data5),
681 6 => Some(Dlsl::Data6),
682 7 => Some(Dlsl::Data7),
683 _ => None,
684 }
685 }
686 #[doc = "Data 0 line signal level"]
687 #[inline(always)]
688 pub fn is_data0(&self) -> bool {
689 *self == Dlsl::Data0
690 }
691 #[doc = "Data 1 line signal level"]
692 #[inline(always)]
693 pub fn is_data1(&self) -> bool {
694 *self == Dlsl::Data1
695 }
696 #[doc = "Data 2 line signal level"]
697 #[inline(always)]
698 pub fn is_data2(&self) -> bool {
699 *self == Dlsl::Data2
700 }
701 #[doc = "Data 3 line signal level"]
702 #[inline(always)]
703 pub fn is_data3(&self) -> bool {
704 *self == Dlsl::Data3
705 }
706 #[doc = "Data 4 line signal level"]
707 #[inline(always)]
708 pub fn is_data4(&self) -> bool {
709 *self == Dlsl::Data4
710 }
711 #[doc = "Data 5 line signal level"]
712 #[inline(always)]
713 pub fn is_data5(&self) -> bool {
714 *self == Dlsl::Data5
715 }
716 #[doc = "Data 6 line signal level"]
717 #[inline(always)]
718 pub fn is_data6(&self) -> bool {
719 *self == Dlsl::Data6
720 }
721 #[doc = "Data 7 line signal level"]
722 #[inline(always)]
723 pub fn is_data7(&self) -> bool {
724 *self == Dlsl::Data7
725 }
726}
727impl R {
728 #[doc = "Bit 0 - Command Inhibit (CMD)"]
729 #[inline(always)]
730 pub fn cihb(&self) -> CihbR {
731 CihbR::new((self.bits & 1) != 0)
732 }
733 #[doc = "Bit 1 - Command Inhibit (DATA)"]
734 #[inline(always)]
735 pub fn cdihb(&self) -> CdihbR {
736 CdihbR::new(((self.bits >> 1) & 1) != 0)
737 }
738 #[doc = "Bit 2 - Data Line Active"]
739 #[inline(always)]
740 pub fn dla(&self) -> DlaR {
741 DlaR::new(((self.bits >> 2) & 1) != 0)
742 }
743 #[doc = "Bit 3 - SD Clock Stable"]
744 #[inline(always)]
745 pub fn sdstb(&self) -> SdstbR {
746 SdstbR::new(((self.bits >> 3) & 1) != 0)
747 }
748 #[doc = "Bit 4 - IPG_CLK Gated Off Internally"]
749 #[inline(always)]
750 pub fn ipgoff(&self) -> IpgoffR {
751 IpgoffR::new(((self.bits >> 4) & 1) != 0)
752 }
753 #[doc = "Bit 5 - HCLK Gated Off Internally"]
754 #[inline(always)]
755 pub fn hckoff(&self) -> HckoffR {
756 HckoffR::new(((self.bits >> 5) & 1) != 0)
757 }
758 #[doc = "Bit 6 - IPG_PERCLK Gated Off Internally"]
759 #[inline(always)]
760 pub fn peroff(&self) -> PeroffR {
761 PeroffR::new(((self.bits >> 6) & 1) != 0)
762 }
763 #[doc = "Bit 7 - SD Clock Gated Off Internally"]
764 #[inline(always)]
765 pub fn sdoff(&self) -> SdoffR {
766 SdoffR::new(((self.bits >> 7) & 1) != 0)
767 }
768 #[doc = "Bit 8 - Write Transfer Active"]
769 #[inline(always)]
770 pub fn wta(&self) -> WtaR {
771 WtaR::new(((self.bits >> 8) & 1) != 0)
772 }
773 #[doc = "Bit 9 - Read Transfer Active"]
774 #[inline(always)]
775 pub fn rta(&self) -> RtaR {
776 RtaR::new(((self.bits >> 9) & 1) != 0)
777 }
778 #[doc = "Bit 10 - Buffer Write Enable"]
779 #[inline(always)]
780 pub fn bwen(&self) -> BwenR {
781 BwenR::new(((self.bits >> 10) & 1) != 0)
782 }
783 #[doc = "Bit 11 - Buffer Read Enable"]
784 #[inline(always)]
785 pub fn bren(&self) -> BrenR {
786 BrenR::new(((self.bits >> 11) & 1) != 0)
787 }
788 #[doc = "Bit 12 - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)"]
789 #[inline(always)]
790 pub fn rtr(&self) -> RtrR {
791 RtrR::new(((self.bits >> 12) & 1) != 0)
792 }
793 #[doc = "Bit 15 - Tape Select Change Done"]
794 #[inline(always)]
795 pub fn tscd(&self) -> TscdR {
796 TscdR::new(((self.bits >> 15) & 1) != 0)
797 }
798 #[doc = "Bit 16 - Card Inserted"]
799 #[inline(always)]
800 pub fn cinst(&self) -> CinstR {
801 CinstR::new(((self.bits >> 16) & 1) != 0)
802 }
803 #[doc = "Bit 18 - Card Detect Pin Level"]
804 #[inline(always)]
805 pub fn cdpl(&self) -> CdplR {
806 CdplR::new(((self.bits >> 18) & 1) != 0)
807 }
808 #[doc = "Bit 19 - Write Protect Switch Pin Level"]
809 #[inline(always)]
810 pub fn wpspl(&self) -> WpsplR {
811 WpsplR::new(((self.bits >> 19) & 1) != 0)
812 }
813 #[doc = "Bit 23 - CMD Line Signal Level"]
814 #[inline(always)]
815 pub fn clsl(&self) -> ClslR {
816 ClslR::new(((self.bits >> 23) & 1) != 0)
817 }
818 #[doc = "Bits 24:31 - DATA\\[7:0\\]
819Line Signal Level"]
820 #[inline(always)]
821 pub fn dlsl(&self) -> DlslR {
822 DlslR::new(((self.bits >> 24) & 0xff) as u8)
823 }
824}
825#[cfg(feature = "debug")]
826impl core::fmt::Debug for R {
827 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
828 f.debug_struct("PRES_STATE")
829 .field("cihb", &self.cihb())
830 .field("cdihb", &self.cdihb())
831 .field("dla", &self.dla())
832 .field("sdstb", &self.sdstb())
833 .field("ipgoff", &self.ipgoff())
834 .field("hckoff", &self.hckoff())
835 .field("peroff", &self.peroff())
836 .field("sdoff", &self.sdoff())
837 .field("wta", &self.wta())
838 .field("rta", &self.rta())
839 .field("bwen", &self.bwen())
840 .field("bren", &self.bren())
841 .field("rtr", &self.rtr())
842 .field("tscd", &self.tscd())
843 .field("cinst", &self.cinst())
844 .field("cdpl", &self.cdpl())
845 .field("wpspl", &self.wpspl())
846 .field("clsl", &self.clsl())
847 .field("dlsl", &self.dlsl())
848 .finish()
849 }
850}
851#[doc = "Present State\n\nYou can [`read`](crate::Reg::read) this register and get [`pres_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
852pub struct PresStateSpec;
853impl crate::RegisterSpec for PresStateSpec {
854 type Ux = u32;
855}
856#[doc = "`read()` method returns [`pres_state::R`](R) reader structure"]
857impl crate::Readable for PresStateSpec {}
858#[doc = "`reset()` method sets PRES_STATE to value 0x8080"]
859impl crate::Resettable for PresStateSpec {
860 const RESET_VALUE: u32 = 0x8080;
861}