mimxrt685s_pac/usart0/
cfg.rs

1#[doc = "Register `CFG` reader"]
2pub type R = crate::R<CfgSpec>;
3#[doc = "Register `CFG` writer"]
4pub type W = crate::W<CfgSpec>;
5#[doc = "USART Enable.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Enable {
9    #[doc = "0: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available."]
10    Disabled = 0,
11    #[doc = "1: Enabled. The USART is enabled for operation."]
12    Enabled = 1,
13}
14impl From<Enable> for bool {
15    #[inline(always)]
16    fn from(variant: Enable) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `ENABLE` reader - USART Enable."]
21pub type EnableR = crate::BitReader<Enable>;
22impl EnableR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Enable {
26        match self.bits {
27            false => Enable::Disabled,
28            true => Enable::Enabled,
29        }
30    }
31    #[doc = "Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available."]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Enable::Disabled
35    }
36    #[doc = "Enabled. The USART is enabled for operation."]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Enable::Enabled
40    }
41}
42#[doc = "Field `ENABLE` writer - USART Enable."]
43pub type EnableW<'a, REG> = crate::BitWriter<'a, REG, Enable>;
44impl<'a, REG> EnableW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available."]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Enable::Disabled)
52    }
53    #[doc = "Enabled. The USART is enabled for operation."]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Enable::Enabled)
57    }
58}
59#[doc = "Selects the data size for the USART.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum Datalen {
64    #[doc = "0: 7 bit Data length."]
65    Bit7 = 0,
66    #[doc = "1: 8 bit Data length."]
67    Bit8 = 1,
68    #[doc = "2: 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register."]
69    Bit9 = 2,
70}
71impl From<Datalen> for u8 {
72    #[inline(always)]
73    fn from(variant: Datalen) -> Self {
74        variant as _
75    }
76}
77impl crate::FieldSpec for Datalen {
78    type Ux = u8;
79}
80impl crate::IsEnum for Datalen {}
81#[doc = "Field `DATALEN` reader - Selects the data size for the USART."]
82pub type DatalenR = crate::FieldReader<Datalen>;
83impl DatalenR {
84    #[doc = "Get enumerated values variant"]
85    #[inline(always)]
86    pub const fn variant(&self) -> Option<Datalen> {
87        match self.bits {
88            0 => Some(Datalen::Bit7),
89            1 => Some(Datalen::Bit8),
90            2 => Some(Datalen::Bit9),
91            _ => None,
92        }
93    }
94    #[doc = "7 bit Data length."]
95    #[inline(always)]
96    pub fn is_bit_7(&self) -> bool {
97        *self == Datalen::Bit7
98    }
99    #[doc = "8 bit Data length."]
100    #[inline(always)]
101    pub fn is_bit_8(&self) -> bool {
102        *self == Datalen::Bit8
103    }
104    #[doc = "9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register."]
105    #[inline(always)]
106    pub fn is_bit_9(&self) -> bool {
107        *self == Datalen::Bit9
108    }
109}
110#[doc = "Field `DATALEN` writer - Selects the data size for the USART."]
111pub type DatalenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Datalen>;
112impl<'a, REG> DatalenW<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115    REG::Ux: From<u8>,
116{
117    #[doc = "7 bit Data length."]
118    #[inline(always)]
119    pub fn bit_7(self) -> &'a mut crate::W<REG> {
120        self.variant(Datalen::Bit7)
121    }
122    #[doc = "8 bit Data length."]
123    #[inline(always)]
124    pub fn bit_8(self) -> &'a mut crate::W<REG> {
125        self.variant(Datalen::Bit8)
126    }
127    #[doc = "9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register."]
128    #[inline(always)]
129    pub fn bit_9(self) -> &'a mut crate::W<REG> {
130        self.variant(Datalen::Bit9)
131    }
132}
133#[doc = "Selects what type of parity is used by the USART.\n\nValue on reset: 0"]
134#[cfg_attr(feature = "defmt", derive(defmt::Format))]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136#[repr(u8)]
137pub enum Paritysel {
138    #[doc = "0: No parity."]
139    NoParity = 0,
140    #[doc = "2: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even."]
141    EvenParity = 2,
142    #[doc = "3: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd."]
143    OddParity = 3,
144}
145impl From<Paritysel> for u8 {
146    #[inline(always)]
147    fn from(variant: Paritysel) -> Self {
148        variant as _
149    }
150}
151impl crate::FieldSpec for Paritysel {
152    type Ux = u8;
153}
154impl crate::IsEnum for Paritysel {}
155#[doc = "Field `PARITYSEL` reader - Selects what type of parity is used by the USART."]
156pub type ParityselR = crate::FieldReader<Paritysel>;
157impl ParityselR {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub const fn variant(&self) -> Option<Paritysel> {
161        match self.bits {
162            0 => Some(Paritysel::NoParity),
163            2 => Some(Paritysel::EvenParity),
164            3 => Some(Paritysel::OddParity),
165            _ => None,
166        }
167    }
168    #[doc = "No parity."]
169    #[inline(always)]
170    pub fn is_no_parity(&self) -> bool {
171        *self == Paritysel::NoParity
172    }
173    #[doc = "Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even."]
174    #[inline(always)]
175    pub fn is_even_parity(&self) -> bool {
176        *self == Paritysel::EvenParity
177    }
178    #[doc = "Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd."]
179    #[inline(always)]
180    pub fn is_odd_parity(&self) -> bool {
181        *self == Paritysel::OddParity
182    }
183}
184#[doc = "Field `PARITYSEL` writer - Selects what type of parity is used by the USART."]
185pub type ParityselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Paritysel>;
186impl<'a, REG> ParityselW<'a, REG>
187where
188    REG: crate::Writable + crate::RegisterSpec,
189    REG::Ux: From<u8>,
190{
191    #[doc = "No parity."]
192    #[inline(always)]
193    pub fn no_parity(self) -> &'a mut crate::W<REG> {
194        self.variant(Paritysel::NoParity)
195    }
196    #[doc = "Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even."]
197    #[inline(always)]
198    pub fn even_parity(self) -> &'a mut crate::W<REG> {
199        self.variant(Paritysel::EvenParity)
200    }
201    #[doc = "Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd."]
202    #[inline(always)]
203    pub fn odd_parity(self) -> &'a mut crate::W<REG> {
204        self.variant(Paritysel::OddParity)
205    }
206}
207#[doc = "Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.\n\nValue on reset: 0"]
208#[cfg_attr(feature = "defmt", derive(defmt::Format))]
209#[derive(Clone, Copy, Debug, PartialEq, Eq)]
210pub enum Stoplen {
211    #[doc = "0: 1 stop bit."]
212    Bit1 = 0,
213    #[doc = "1: 2 stop bits. This setting should only be used for asynchronous communication."]
214    Bits2 = 1,
215}
216impl From<Stoplen> for bool {
217    #[inline(always)]
218    fn from(variant: Stoplen) -> Self {
219        variant as u8 != 0
220    }
221}
222#[doc = "Field `STOPLEN` reader - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
223pub type StoplenR = crate::BitReader<Stoplen>;
224impl StoplenR {
225    #[doc = "Get enumerated values variant"]
226    #[inline(always)]
227    pub const fn variant(&self) -> Stoplen {
228        match self.bits {
229            false => Stoplen::Bit1,
230            true => Stoplen::Bits2,
231        }
232    }
233    #[doc = "1 stop bit."]
234    #[inline(always)]
235    pub fn is_bit_1(&self) -> bool {
236        *self == Stoplen::Bit1
237    }
238    #[doc = "2 stop bits. This setting should only be used for asynchronous communication."]
239    #[inline(always)]
240    pub fn is_bits_2(&self) -> bool {
241        *self == Stoplen::Bits2
242    }
243}
244#[doc = "Field `STOPLEN` writer - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
245pub type StoplenW<'a, REG> = crate::BitWriter<'a, REG, Stoplen>;
246impl<'a, REG> StoplenW<'a, REG>
247where
248    REG: crate::Writable + crate::RegisterSpec,
249{
250    #[doc = "1 stop bit."]
251    #[inline(always)]
252    pub fn bit_1(self) -> &'a mut crate::W<REG> {
253        self.variant(Stoplen::Bit1)
254    }
255    #[doc = "2 stop bits. This setting should only be used for asynchronous communication."]
256    #[inline(always)]
257    pub fn bits_2(self) -> &'a mut crate::W<REG> {
258        self.variant(Stoplen::Bits2)
259    }
260}
261#[doc = "Selects standard or 32 kHz clocking mode.\n\nValue on reset: 0"]
262#[cfg_attr(feature = "defmt", derive(defmt::Format))]
263#[derive(Clone, Copy, Debug, PartialEq, Eq)]
264pub enum Mode32k {
265    #[doc = "0: Disabled. USART uses standard clocking."]
266    Disabled = 0,
267    #[doc = "1: Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme."]
268    Enabled = 1,
269}
270impl From<Mode32k> for bool {
271    #[inline(always)]
272    fn from(variant: Mode32k) -> Self {
273        variant as u8 != 0
274    }
275}
276#[doc = "Field `MODE32K` reader - Selects standard or 32 kHz clocking mode."]
277pub type Mode32kR = crate::BitReader<Mode32k>;
278impl Mode32kR {
279    #[doc = "Get enumerated values variant"]
280    #[inline(always)]
281    pub const fn variant(&self) -> Mode32k {
282        match self.bits {
283            false => Mode32k::Disabled,
284            true => Mode32k::Enabled,
285        }
286    }
287    #[doc = "Disabled. USART uses standard clocking."]
288    #[inline(always)]
289    pub fn is_disabled(&self) -> bool {
290        *self == Mode32k::Disabled
291    }
292    #[doc = "Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme."]
293    #[inline(always)]
294    pub fn is_enabled(&self) -> bool {
295        *self == Mode32k::Enabled
296    }
297}
298#[doc = "Field `MODE32K` writer - Selects standard or 32 kHz clocking mode."]
299pub type Mode32kW<'a, REG> = crate::BitWriter<'a, REG, Mode32k>;
300impl<'a, REG> Mode32kW<'a, REG>
301where
302    REG: crate::Writable + crate::RegisterSpec,
303{
304    #[doc = "Disabled. USART uses standard clocking."]
305    #[inline(always)]
306    pub fn disabled(self) -> &'a mut crate::W<REG> {
307        self.variant(Mode32k::Disabled)
308    }
309    #[doc = "Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme."]
310    #[inline(always)]
311    pub fn enabled(self) -> &'a mut crate::W<REG> {
312        self.variant(Mode32k::Enabled)
313    }
314}
315#[doc = "LIN break mode enable.\n\nValue on reset: 0"]
316#[cfg_attr(feature = "defmt", derive(defmt::Format))]
317#[derive(Clone, Copy, Debug, PartialEq, Eq)]
318pub enum Linmode {
319    #[doc = "0: Disabled. Break detect and generate is configured for normal operation."]
320    Disabled = 0,
321    #[doc = "1: Enabled. Break detect and generate is configured for LIN bus operation."]
322    Enabled = 1,
323}
324impl From<Linmode> for bool {
325    #[inline(always)]
326    fn from(variant: Linmode) -> Self {
327        variant as u8 != 0
328    }
329}
330#[doc = "Field `LINMODE` reader - LIN break mode enable."]
331pub type LinmodeR = crate::BitReader<Linmode>;
332impl LinmodeR {
333    #[doc = "Get enumerated values variant"]
334    #[inline(always)]
335    pub const fn variant(&self) -> Linmode {
336        match self.bits {
337            false => Linmode::Disabled,
338            true => Linmode::Enabled,
339        }
340    }
341    #[doc = "Disabled. Break detect and generate is configured for normal operation."]
342    #[inline(always)]
343    pub fn is_disabled(&self) -> bool {
344        *self == Linmode::Disabled
345    }
346    #[doc = "Enabled. Break detect and generate is configured for LIN bus operation."]
347    #[inline(always)]
348    pub fn is_enabled(&self) -> bool {
349        *self == Linmode::Enabled
350    }
351}
352#[doc = "Field `LINMODE` writer - LIN break mode enable."]
353pub type LinmodeW<'a, REG> = crate::BitWriter<'a, REG, Linmode>;
354impl<'a, REG> LinmodeW<'a, REG>
355where
356    REG: crate::Writable + crate::RegisterSpec,
357{
358    #[doc = "Disabled. Break detect and generate is configured for normal operation."]
359    #[inline(always)]
360    pub fn disabled(self) -> &'a mut crate::W<REG> {
361        self.variant(Linmode::Disabled)
362    }
363    #[doc = "Enabled. Break detect and generate is configured for LIN bus operation."]
364    #[inline(always)]
365    pub fn enabled(self) -> &'a mut crate::W<REG> {
366        self.variant(Linmode::Enabled)
367    }
368}
369#[doc = "CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.\n\nValue on reset: 0"]
370#[cfg_attr(feature = "defmt", derive(defmt::Format))]
371#[derive(Clone, Copy, Debug, PartialEq, Eq)]
372pub enum Ctsen {
373    #[doc = "0: No flow control. The transmitter does not receive any automatic flow control signal."]
374    Disabled = 0,
375    #[doc = "1: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes."]
376    Enabled = 1,
377}
378impl From<Ctsen> for bool {
379    #[inline(always)]
380    fn from(variant: Ctsen) -> Self {
381        variant as u8 != 0
382    }
383}
384#[doc = "Field `CTSEN` reader - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
385pub type CtsenR = crate::BitReader<Ctsen>;
386impl CtsenR {
387    #[doc = "Get enumerated values variant"]
388    #[inline(always)]
389    pub const fn variant(&self) -> Ctsen {
390        match self.bits {
391            false => Ctsen::Disabled,
392            true => Ctsen::Enabled,
393        }
394    }
395    #[doc = "No flow control. The transmitter does not receive any automatic flow control signal."]
396    #[inline(always)]
397    pub fn is_disabled(&self) -> bool {
398        *self == Ctsen::Disabled
399    }
400    #[doc = "Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes."]
401    #[inline(always)]
402    pub fn is_enabled(&self) -> bool {
403        *self == Ctsen::Enabled
404    }
405}
406#[doc = "Field `CTSEN` writer - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
407pub type CtsenW<'a, REG> = crate::BitWriter<'a, REG, Ctsen>;
408impl<'a, REG> CtsenW<'a, REG>
409where
410    REG: crate::Writable + crate::RegisterSpec,
411{
412    #[doc = "No flow control. The transmitter does not receive any automatic flow control signal."]
413    #[inline(always)]
414    pub fn disabled(self) -> &'a mut crate::W<REG> {
415        self.variant(Ctsen::Disabled)
416    }
417    #[doc = "Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes."]
418    #[inline(always)]
419    pub fn enabled(self) -> &'a mut crate::W<REG> {
420        self.variant(Ctsen::Enabled)
421    }
422}
423#[doc = "Selects synchronous or asynchronous operation.\n\nValue on reset: 0"]
424#[cfg_attr(feature = "defmt", derive(defmt::Format))]
425#[derive(Clone, Copy, Debug, PartialEq, Eq)]
426pub enum Syncen {
427    #[doc = "0: Asynchronous mode."]
428    AsynchronousMode = 0,
429    #[doc = "1: Synchronous mode."]
430    SynchronousMode = 1,
431}
432impl From<Syncen> for bool {
433    #[inline(always)]
434    fn from(variant: Syncen) -> Self {
435        variant as u8 != 0
436    }
437}
438#[doc = "Field `SYNCEN` reader - Selects synchronous or asynchronous operation."]
439pub type SyncenR = crate::BitReader<Syncen>;
440impl SyncenR {
441    #[doc = "Get enumerated values variant"]
442    #[inline(always)]
443    pub const fn variant(&self) -> Syncen {
444        match self.bits {
445            false => Syncen::AsynchronousMode,
446            true => Syncen::SynchronousMode,
447        }
448    }
449    #[doc = "Asynchronous mode."]
450    #[inline(always)]
451    pub fn is_asynchronous_mode(&self) -> bool {
452        *self == Syncen::AsynchronousMode
453    }
454    #[doc = "Synchronous mode."]
455    #[inline(always)]
456    pub fn is_synchronous_mode(&self) -> bool {
457        *self == Syncen::SynchronousMode
458    }
459}
460#[doc = "Field `SYNCEN` writer - Selects synchronous or asynchronous operation."]
461pub type SyncenW<'a, REG> = crate::BitWriter<'a, REG, Syncen>;
462impl<'a, REG> SyncenW<'a, REG>
463where
464    REG: crate::Writable + crate::RegisterSpec,
465{
466    #[doc = "Asynchronous mode."]
467    #[inline(always)]
468    pub fn asynchronous_mode(self) -> &'a mut crate::W<REG> {
469        self.variant(Syncen::AsynchronousMode)
470    }
471    #[doc = "Synchronous mode."]
472    #[inline(always)]
473    pub fn synchronous_mode(self) -> &'a mut crate::W<REG> {
474        self.variant(Syncen::SynchronousMode)
475    }
476}
477#[doc = "Selects the clock polarity and sampling edge of received data in synchronous mode.\n\nValue on reset: 0"]
478#[cfg_attr(feature = "defmt", derive(defmt::Format))]
479#[derive(Clone, Copy, Debug, PartialEq, Eq)]
480pub enum Clkpol {
481    #[doc = "0: Falling edge. Un_RXD is sampled on the falling edge of SCLK."]
482    FallingEdge = 0,
483    #[doc = "1: Rising edge. Un_RXD is sampled on the rising edge of SCLK."]
484    RisingEdge = 1,
485}
486impl From<Clkpol> for bool {
487    #[inline(always)]
488    fn from(variant: Clkpol) -> Self {
489        variant as u8 != 0
490    }
491}
492#[doc = "Field `CLKPOL` reader - Selects the clock polarity and sampling edge of received data in synchronous mode."]
493pub type ClkpolR = crate::BitReader<Clkpol>;
494impl ClkpolR {
495    #[doc = "Get enumerated values variant"]
496    #[inline(always)]
497    pub const fn variant(&self) -> Clkpol {
498        match self.bits {
499            false => Clkpol::FallingEdge,
500            true => Clkpol::RisingEdge,
501        }
502    }
503    #[doc = "Falling edge. Un_RXD is sampled on the falling edge of SCLK."]
504    #[inline(always)]
505    pub fn is_falling_edge(&self) -> bool {
506        *self == Clkpol::FallingEdge
507    }
508    #[doc = "Rising edge. Un_RXD is sampled on the rising edge of SCLK."]
509    #[inline(always)]
510    pub fn is_rising_edge(&self) -> bool {
511        *self == Clkpol::RisingEdge
512    }
513}
514#[doc = "Field `CLKPOL` writer - Selects the clock polarity and sampling edge of received data in synchronous mode."]
515pub type ClkpolW<'a, REG> = crate::BitWriter<'a, REG, Clkpol>;
516impl<'a, REG> ClkpolW<'a, REG>
517where
518    REG: crate::Writable + crate::RegisterSpec,
519{
520    #[doc = "Falling edge. Un_RXD is sampled on the falling edge of SCLK."]
521    #[inline(always)]
522    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
523        self.variant(Clkpol::FallingEdge)
524    }
525    #[doc = "Rising edge. Un_RXD is sampled on the rising edge of SCLK."]
526    #[inline(always)]
527    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
528        self.variant(Clkpol::RisingEdge)
529    }
530}
531#[doc = "Synchronous mode Master select.\n\nValue on reset: 0"]
532#[cfg_attr(feature = "defmt", derive(defmt::Format))]
533#[derive(Clone, Copy, Debug, PartialEq, Eq)]
534pub enum Syncmst {
535    #[doc = "0: Slave. When synchronous mode is enabled, the USART is a slave."]
536    Slave = 0,
537    #[doc = "1: Master. When synchronous mode is enabled, the USART is a master."]
538    Master = 1,
539}
540impl From<Syncmst> for bool {
541    #[inline(always)]
542    fn from(variant: Syncmst) -> Self {
543        variant as u8 != 0
544    }
545}
546#[doc = "Field `SYNCMST` reader - Synchronous mode Master select."]
547pub type SyncmstR = crate::BitReader<Syncmst>;
548impl SyncmstR {
549    #[doc = "Get enumerated values variant"]
550    #[inline(always)]
551    pub const fn variant(&self) -> Syncmst {
552        match self.bits {
553            false => Syncmst::Slave,
554            true => Syncmst::Master,
555        }
556    }
557    #[doc = "Slave. When synchronous mode is enabled, the USART is a slave."]
558    #[inline(always)]
559    pub fn is_slave(&self) -> bool {
560        *self == Syncmst::Slave
561    }
562    #[doc = "Master. When synchronous mode is enabled, the USART is a master."]
563    #[inline(always)]
564    pub fn is_master(&self) -> bool {
565        *self == Syncmst::Master
566    }
567}
568#[doc = "Field `SYNCMST` writer - Synchronous mode Master select."]
569pub type SyncmstW<'a, REG> = crate::BitWriter<'a, REG, Syncmst>;
570impl<'a, REG> SyncmstW<'a, REG>
571where
572    REG: crate::Writable + crate::RegisterSpec,
573{
574    #[doc = "Slave. When synchronous mode is enabled, the USART is a slave."]
575    #[inline(always)]
576    pub fn slave(self) -> &'a mut crate::W<REG> {
577        self.variant(Syncmst::Slave)
578    }
579    #[doc = "Master. When synchronous mode is enabled, the USART is a master."]
580    #[inline(always)]
581    pub fn master(self) -> &'a mut crate::W<REG> {
582        self.variant(Syncmst::Master)
583    }
584}
585#[doc = "Selects data loopback mode.\n\nValue on reset: 0"]
586#[cfg_attr(feature = "defmt", derive(defmt::Format))]
587#[derive(Clone, Copy, Debug, PartialEq, Eq)]
588pub enum Loop {
589    #[doc = "0: Normal operation."]
590    Normal = 0,
591    #[doc = "1: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN."]
592    Loopback = 1,
593}
594impl From<Loop> for bool {
595    #[inline(always)]
596    fn from(variant: Loop) -> Self {
597        variant as u8 != 0
598    }
599}
600#[doc = "Field `LOOP` reader - Selects data loopback mode."]
601pub type LoopR = crate::BitReader<Loop>;
602impl LoopR {
603    #[doc = "Get enumerated values variant"]
604    #[inline(always)]
605    pub const fn variant(&self) -> Loop {
606        match self.bits {
607            false => Loop::Normal,
608            true => Loop::Loopback,
609        }
610    }
611    #[doc = "Normal operation."]
612    #[inline(always)]
613    pub fn is_normal(&self) -> bool {
614        *self == Loop::Normal
615    }
616    #[doc = "Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN."]
617    #[inline(always)]
618    pub fn is_loopback(&self) -> bool {
619        *self == Loop::Loopback
620    }
621}
622#[doc = "Field `LOOP` writer - Selects data loopback mode."]
623pub type LoopW<'a, REG> = crate::BitWriter<'a, REG, Loop>;
624impl<'a, REG> LoopW<'a, REG>
625where
626    REG: crate::Writable + crate::RegisterSpec,
627{
628    #[doc = "Normal operation."]
629    #[inline(always)]
630    pub fn normal(self) -> &'a mut crate::W<REG> {
631        self.variant(Loop::Normal)
632    }
633    #[doc = "Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN."]
634    #[inline(always)]
635    pub fn loopback(self) -> &'a mut crate::W<REG> {
636        self.variant(Loop::Loopback)
637    }
638}
639#[doc = "Output Enable Turnaround time enable for RS-485 operation.\n\nValue on reset: 0"]
640#[cfg_attr(feature = "defmt", derive(defmt::Format))]
641#[derive(Clone, Copy, Debug, PartialEq, Eq)]
642pub enum Oeta {
643    #[doc = "0: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission."]
644    Disabled = 0,
645    #[doc = "1: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted."]
646    Enabled = 1,
647}
648impl From<Oeta> for bool {
649    #[inline(always)]
650    fn from(variant: Oeta) -> Self {
651        variant as u8 != 0
652    }
653}
654#[doc = "Field `OETA` reader - Output Enable Turnaround time enable for RS-485 operation."]
655pub type OetaR = crate::BitReader<Oeta>;
656impl OetaR {
657    #[doc = "Get enumerated values variant"]
658    #[inline(always)]
659    pub const fn variant(&self) -> Oeta {
660        match self.bits {
661            false => Oeta::Disabled,
662            true => Oeta::Enabled,
663        }
664    }
665    #[doc = "Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission."]
666    #[inline(always)]
667    pub fn is_disabled(&self) -> bool {
668        *self == Oeta::Disabled
669    }
670    #[doc = "Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted."]
671    #[inline(always)]
672    pub fn is_enabled(&self) -> bool {
673        *self == Oeta::Enabled
674    }
675}
676#[doc = "Field `OETA` writer - Output Enable Turnaround time enable for RS-485 operation."]
677pub type OetaW<'a, REG> = crate::BitWriter<'a, REG, Oeta>;
678impl<'a, REG> OetaW<'a, REG>
679where
680    REG: crate::Writable + crate::RegisterSpec,
681{
682    #[doc = "Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission."]
683    #[inline(always)]
684    pub fn disabled(self) -> &'a mut crate::W<REG> {
685        self.variant(Oeta::Disabled)
686    }
687    #[doc = "Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted."]
688    #[inline(always)]
689    pub fn enabled(self) -> &'a mut crate::W<REG> {
690        self.variant(Oeta::Enabled)
691    }
692}
693#[doc = "Automatic Address matching enable.\n\nValue on reset: 0"]
694#[cfg_attr(feature = "defmt", derive(defmt::Format))]
695#[derive(Clone, Copy, Debug, PartialEq, Eq)]
696pub enum Autoaddr {
697    #[doc = "0: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)."]
698    Disabled = 0,
699    #[doc = "1: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match."]
700    Enabled = 1,
701}
702impl From<Autoaddr> for bool {
703    #[inline(always)]
704    fn from(variant: Autoaddr) -> Self {
705        variant as u8 != 0
706    }
707}
708#[doc = "Field `AUTOADDR` reader - Automatic Address matching enable."]
709pub type AutoaddrR = crate::BitReader<Autoaddr>;
710impl AutoaddrR {
711    #[doc = "Get enumerated values variant"]
712    #[inline(always)]
713    pub const fn variant(&self) -> Autoaddr {
714        match self.bits {
715            false => Autoaddr::Disabled,
716            true => Autoaddr::Enabled,
717        }
718    }
719    #[doc = "Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)."]
720    #[inline(always)]
721    pub fn is_disabled(&self) -> bool {
722        *self == Autoaddr::Disabled
723    }
724    #[doc = "Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match."]
725    #[inline(always)]
726    pub fn is_enabled(&self) -> bool {
727        *self == Autoaddr::Enabled
728    }
729}
730#[doc = "Field `AUTOADDR` writer - Automatic Address matching enable."]
731pub type AutoaddrW<'a, REG> = crate::BitWriter<'a, REG, Autoaddr>;
732impl<'a, REG> AutoaddrW<'a, REG>
733where
734    REG: crate::Writable + crate::RegisterSpec,
735{
736    #[doc = "Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)."]
737    #[inline(always)]
738    pub fn disabled(self) -> &'a mut crate::W<REG> {
739        self.variant(Autoaddr::Disabled)
740    }
741    #[doc = "Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match."]
742    #[inline(always)]
743    pub fn enabled(self) -> &'a mut crate::W<REG> {
744        self.variant(Autoaddr::Enabled)
745    }
746}
747#[doc = "Output Enable Select.\n\nValue on reset: 0"]
748#[cfg_attr(feature = "defmt", derive(defmt::Format))]
749#[derive(Clone, Copy, Debug, PartialEq, Eq)]
750pub enum Oesel {
751    #[doc = "0: Standard. The RTS signal is used as the standard flow control function."]
752    Standard = 0,
753    #[doc = "1: RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver."]
754    Rs485 = 1,
755}
756impl From<Oesel> for bool {
757    #[inline(always)]
758    fn from(variant: Oesel) -> Self {
759        variant as u8 != 0
760    }
761}
762#[doc = "Field `OESEL` reader - Output Enable Select."]
763pub type OeselR = crate::BitReader<Oesel>;
764impl OeselR {
765    #[doc = "Get enumerated values variant"]
766    #[inline(always)]
767    pub const fn variant(&self) -> Oesel {
768        match self.bits {
769            false => Oesel::Standard,
770            true => Oesel::Rs485,
771        }
772    }
773    #[doc = "Standard. The RTS signal is used as the standard flow control function."]
774    #[inline(always)]
775    pub fn is_standard(&self) -> bool {
776        *self == Oesel::Standard
777    }
778    #[doc = "RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver."]
779    #[inline(always)]
780    pub fn is_rs_485(&self) -> bool {
781        *self == Oesel::Rs485
782    }
783}
784#[doc = "Field `OESEL` writer - Output Enable Select."]
785pub type OeselW<'a, REG> = crate::BitWriter<'a, REG, Oesel>;
786impl<'a, REG> OeselW<'a, REG>
787where
788    REG: crate::Writable + crate::RegisterSpec,
789{
790    #[doc = "Standard. The RTS signal is used as the standard flow control function."]
791    #[inline(always)]
792    pub fn standard(self) -> &'a mut crate::W<REG> {
793        self.variant(Oesel::Standard)
794    }
795    #[doc = "RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver."]
796    #[inline(always)]
797    pub fn rs_485(self) -> &'a mut crate::W<REG> {
798        self.variant(Oesel::Rs485)
799    }
800}
801#[doc = "Output Enable Polarity.\n\nValue on reset: 0"]
802#[cfg_attr(feature = "defmt", derive(defmt::Format))]
803#[derive(Clone, Copy, Debug, PartialEq, Eq)]
804pub enum Oepol {
805    #[doc = "0: Low. If selected by OESEL, the output enable is active low."]
806    Low = 0,
807    #[doc = "1: High. If selected by OESEL, the output enable is active high."]
808    High = 1,
809}
810impl From<Oepol> for bool {
811    #[inline(always)]
812    fn from(variant: Oepol) -> Self {
813        variant as u8 != 0
814    }
815}
816#[doc = "Field `OEPOL` reader - Output Enable Polarity."]
817pub type OepolR = crate::BitReader<Oepol>;
818impl OepolR {
819    #[doc = "Get enumerated values variant"]
820    #[inline(always)]
821    pub const fn variant(&self) -> Oepol {
822        match self.bits {
823            false => Oepol::Low,
824            true => Oepol::High,
825        }
826    }
827    #[doc = "Low. If selected by OESEL, the output enable is active low."]
828    #[inline(always)]
829    pub fn is_low(&self) -> bool {
830        *self == Oepol::Low
831    }
832    #[doc = "High. If selected by OESEL, the output enable is active high."]
833    #[inline(always)]
834    pub fn is_high(&self) -> bool {
835        *self == Oepol::High
836    }
837}
838#[doc = "Field `OEPOL` writer - Output Enable Polarity."]
839pub type OepolW<'a, REG> = crate::BitWriter<'a, REG, Oepol>;
840impl<'a, REG> OepolW<'a, REG>
841where
842    REG: crate::Writable + crate::RegisterSpec,
843{
844    #[doc = "Low. If selected by OESEL, the output enable is active low."]
845    #[inline(always)]
846    pub fn low(self) -> &'a mut crate::W<REG> {
847        self.variant(Oepol::Low)
848    }
849    #[doc = "High. If selected by OESEL, the output enable is active high."]
850    #[inline(always)]
851    pub fn high(self) -> &'a mut crate::W<REG> {
852        self.variant(Oepol::High)
853    }
854}
855#[doc = "Receive data polarity.\n\nValue on reset: 0"]
856#[cfg_attr(feature = "defmt", derive(defmt::Format))]
857#[derive(Clone, Copy, Debug, PartialEq, Eq)]
858pub enum Rxpol {
859    #[doc = "0: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
860    Standard = 0,
861    #[doc = "1: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
862    Inverted = 1,
863}
864impl From<Rxpol> for bool {
865    #[inline(always)]
866    fn from(variant: Rxpol) -> Self {
867        variant as u8 != 0
868    }
869}
870#[doc = "Field `RXPOL` reader - Receive data polarity."]
871pub type RxpolR = crate::BitReader<Rxpol>;
872impl RxpolR {
873    #[doc = "Get enumerated values variant"]
874    #[inline(always)]
875    pub const fn variant(&self) -> Rxpol {
876        match self.bits {
877            false => Rxpol::Standard,
878            true => Rxpol::Inverted,
879        }
880    }
881    #[doc = "Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
882    #[inline(always)]
883    pub fn is_standard(&self) -> bool {
884        *self == Rxpol::Standard
885    }
886    #[doc = "Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
887    #[inline(always)]
888    pub fn is_inverted(&self) -> bool {
889        *self == Rxpol::Inverted
890    }
891}
892#[doc = "Field `RXPOL` writer - Receive data polarity."]
893pub type RxpolW<'a, REG> = crate::BitWriter<'a, REG, Rxpol>;
894impl<'a, REG> RxpolW<'a, REG>
895where
896    REG: crate::Writable + crate::RegisterSpec,
897{
898    #[doc = "Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
899    #[inline(always)]
900    pub fn standard(self) -> &'a mut crate::W<REG> {
901        self.variant(Rxpol::Standard)
902    }
903    #[doc = "Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
904    #[inline(always)]
905    pub fn inverted(self) -> &'a mut crate::W<REG> {
906        self.variant(Rxpol::Inverted)
907    }
908}
909#[doc = "Transmit data polarity.\n\nValue on reset: 0"]
910#[cfg_attr(feature = "defmt", derive(defmt::Format))]
911#[derive(Clone, Copy, Debug, PartialEq, Eq)]
912pub enum Txpol {
913    #[doc = "0: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
914    Standard = 0,
915    #[doc = "1: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
916    Inverted = 1,
917}
918impl From<Txpol> for bool {
919    #[inline(always)]
920    fn from(variant: Txpol) -> Self {
921        variant as u8 != 0
922    }
923}
924#[doc = "Field `TXPOL` reader - Transmit data polarity."]
925pub type TxpolR = crate::BitReader<Txpol>;
926impl TxpolR {
927    #[doc = "Get enumerated values variant"]
928    #[inline(always)]
929    pub const fn variant(&self) -> Txpol {
930        match self.bits {
931            false => Txpol::Standard,
932            true => Txpol::Inverted,
933        }
934    }
935    #[doc = "Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
936    #[inline(always)]
937    pub fn is_standard(&self) -> bool {
938        *self == Txpol::Standard
939    }
940    #[doc = "Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
941    #[inline(always)]
942    pub fn is_inverted(&self) -> bool {
943        *self == Txpol::Inverted
944    }
945}
946#[doc = "Field `TXPOL` writer - Transmit data polarity."]
947pub type TxpolW<'a, REG> = crate::BitWriter<'a, REG, Txpol>;
948impl<'a, REG> TxpolW<'a, REG>
949where
950    REG: crate::Writable + crate::RegisterSpec,
951{
952    #[doc = "Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
953    #[inline(always)]
954    pub fn standard(self) -> &'a mut crate::W<REG> {
955        self.variant(Txpol::Standard)
956    }
957    #[doc = "Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
958    #[inline(always)]
959    pub fn inverted(self) -> &'a mut crate::W<REG> {
960        self.variant(Txpol::Inverted)
961    }
962}
963impl R {
964    #[doc = "Bit 0 - USART Enable."]
965    #[inline(always)]
966    pub fn enable(&self) -> EnableR {
967        EnableR::new((self.bits & 1) != 0)
968    }
969    #[doc = "Bits 2:3 - Selects the data size for the USART."]
970    #[inline(always)]
971    pub fn datalen(&self) -> DatalenR {
972        DatalenR::new(((self.bits >> 2) & 3) as u8)
973    }
974    #[doc = "Bits 4:5 - Selects what type of parity is used by the USART."]
975    #[inline(always)]
976    pub fn paritysel(&self) -> ParityselR {
977        ParityselR::new(((self.bits >> 4) & 3) as u8)
978    }
979    #[doc = "Bit 6 - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
980    #[inline(always)]
981    pub fn stoplen(&self) -> StoplenR {
982        StoplenR::new(((self.bits >> 6) & 1) != 0)
983    }
984    #[doc = "Bit 7 - Selects standard or 32 kHz clocking mode."]
985    #[inline(always)]
986    pub fn mode32k(&self) -> Mode32kR {
987        Mode32kR::new(((self.bits >> 7) & 1) != 0)
988    }
989    #[doc = "Bit 8 - LIN break mode enable."]
990    #[inline(always)]
991    pub fn linmode(&self) -> LinmodeR {
992        LinmodeR::new(((self.bits >> 8) & 1) != 0)
993    }
994    #[doc = "Bit 9 - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
995    #[inline(always)]
996    pub fn ctsen(&self) -> CtsenR {
997        CtsenR::new(((self.bits >> 9) & 1) != 0)
998    }
999    #[doc = "Bit 11 - Selects synchronous or asynchronous operation."]
1000    #[inline(always)]
1001    pub fn syncen(&self) -> SyncenR {
1002        SyncenR::new(((self.bits >> 11) & 1) != 0)
1003    }
1004    #[doc = "Bit 12 - Selects the clock polarity and sampling edge of received data in synchronous mode."]
1005    #[inline(always)]
1006    pub fn clkpol(&self) -> ClkpolR {
1007        ClkpolR::new(((self.bits >> 12) & 1) != 0)
1008    }
1009    #[doc = "Bit 14 - Synchronous mode Master select."]
1010    #[inline(always)]
1011    pub fn syncmst(&self) -> SyncmstR {
1012        SyncmstR::new(((self.bits >> 14) & 1) != 0)
1013    }
1014    #[doc = "Bit 15 - Selects data loopback mode."]
1015    #[inline(always)]
1016    pub fn loop_(&self) -> LoopR {
1017        LoopR::new(((self.bits >> 15) & 1) != 0)
1018    }
1019    #[doc = "Bit 18 - Output Enable Turnaround time enable for RS-485 operation."]
1020    #[inline(always)]
1021    pub fn oeta(&self) -> OetaR {
1022        OetaR::new(((self.bits >> 18) & 1) != 0)
1023    }
1024    #[doc = "Bit 19 - Automatic Address matching enable."]
1025    #[inline(always)]
1026    pub fn autoaddr(&self) -> AutoaddrR {
1027        AutoaddrR::new(((self.bits >> 19) & 1) != 0)
1028    }
1029    #[doc = "Bit 20 - Output Enable Select."]
1030    #[inline(always)]
1031    pub fn oesel(&self) -> OeselR {
1032        OeselR::new(((self.bits >> 20) & 1) != 0)
1033    }
1034    #[doc = "Bit 21 - Output Enable Polarity."]
1035    #[inline(always)]
1036    pub fn oepol(&self) -> OepolR {
1037        OepolR::new(((self.bits >> 21) & 1) != 0)
1038    }
1039    #[doc = "Bit 22 - Receive data polarity."]
1040    #[inline(always)]
1041    pub fn rxpol(&self) -> RxpolR {
1042        RxpolR::new(((self.bits >> 22) & 1) != 0)
1043    }
1044    #[doc = "Bit 23 - Transmit data polarity."]
1045    #[inline(always)]
1046    pub fn txpol(&self) -> TxpolR {
1047        TxpolR::new(((self.bits >> 23) & 1) != 0)
1048    }
1049}
1050#[cfg(feature = "debug")]
1051impl core::fmt::Debug for R {
1052    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1053        f.debug_struct("CFG")
1054            .field("enable", &self.enable())
1055            .field("datalen", &self.datalen())
1056            .field("paritysel", &self.paritysel())
1057            .field("stoplen", &self.stoplen())
1058            .field("mode32k", &self.mode32k())
1059            .field("linmode", &self.linmode())
1060            .field("ctsen", &self.ctsen())
1061            .field("syncen", &self.syncen())
1062            .field("clkpol", &self.clkpol())
1063            .field("syncmst", &self.syncmst())
1064            .field("loop_", &self.loop_())
1065            .field("oeta", &self.oeta())
1066            .field("autoaddr", &self.autoaddr())
1067            .field("oesel", &self.oesel())
1068            .field("oepol", &self.oepol())
1069            .field("rxpol", &self.rxpol())
1070            .field("txpol", &self.txpol())
1071            .finish()
1072    }
1073}
1074impl W {
1075    #[doc = "Bit 0 - USART Enable."]
1076    #[inline(always)]
1077    pub fn enable(&mut self) -> EnableW<CfgSpec> {
1078        EnableW::new(self, 0)
1079    }
1080    #[doc = "Bits 2:3 - Selects the data size for the USART."]
1081    #[inline(always)]
1082    pub fn datalen(&mut self) -> DatalenW<CfgSpec> {
1083        DatalenW::new(self, 2)
1084    }
1085    #[doc = "Bits 4:5 - Selects what type of parity is used by the USART."]
1086    #[inline(always)]
1087    pub fn paritysel(&mut self) -> ParityselW<CfgSpec> {
1088        ParityselW::new(self, 4)
1089    }
1090    #[doc = "Bit 6 - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
1091    #[inline(always)]
1092    pub fn stoplen(&mut self) -> StoplenW<CfgSpec> {
1093        StoplenW::new(self, 6)
1094    }
1095    #[doc = "Bit 7 - Selects standard or 32 kHz clocking mode."]
1096    #[inline(always)]
1097    pub fn mode32k(&mut self) -> Mode32kW<CfgSpec> {
1098        Mode32kW::new(self, 7)
1099    }
1100    #[doc = "Bit 8 - LIN break mode enable."]
1101    #[inline(always)]
1102    pub fn linmode(&mut self) -> LinmodeW<CfgSpec> {
1103        LinmodeW::new(self, 8)
1104    }
1105    #[doc = "Bit 9 - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
1106    #[inline(always)]
1107    pub fn ctsen(&mut self) -> CtsenW<CfgSpec> {
1108        CtsenW::new(self, 9)
1109    }
1110    #[doc = "Bit 11 - Selects synchronous or asynchronous operation."]
1111    #[inline(always)]
1112    pub fn syncen(&mut self) -> SyncenW<CfgSpec> {
1113        SyncenW::new(self, 11)
1114    }
1115    #[doc = "Bit 12 - Selects the clock polarity and sampling edge of received data in synchronous mode."]
1116    #[inline(always)]
1117    pub fn clkpol(&mut self) -> ClkpolW<CfgSpec> {
1118        ClkpolW::new(self, 12)
1119    }
1120    #[doc = "Bit 14 - Synchronous mode Master select."]
1121    #[inline(always)]
1122    pub fn syncmst(&mut self) -> SyncmstW<CfgSpec> {
1123        SyncmstW::new(self, 14)
1124    }
1125    #[doc = "Bit 15 - Selects data loopback mode."]
1126    #[inline(always)]
1127    pub fn loop_(&mut self) -> LoopW<CfgSpec> {
1128        LoopW::new(self, 15)
1129    }
1130    #[doc = "Bit 18 - Output Enable Turnaround time enable for RS-485 operation."]
1131    #[inline(always)]
1132    pub fn oeta(&mut self) -> OetaW<CfgSpec> {
1133        OetaW::new(self, 18)
1134    }
1135    #[doc = "Bit 19 - Automatic Address matching enable."]
1136    #[inline(always)]
1137    pub fn autoaddr(&mut self) -> AutoaddrW<CfgSpec> {
1138        AutoaddrW::new(self, 19)
1139    }
1140    #[doc = "Bit 20 - Output Enable Select."]
1141    #[inline(always)]
1142    pub fn oesel(&mut self) -> OeselW<CfgSpec> {
1143        OeselW::new(self, 20)
1144    }
1145    #[doc = "Bit 21 - Output Enable Polarity."]
1146    #[inline(always)]
1147    pub fn oepol(&mut self) -> OepolW<CfgSpec> {
1148        OepolW::new(self, 21)
1149    }
1150    #[doc = "Bit 22 - Receive data polarity."]
1151    #[inline(always)]
1152    pub fn rxpol(&mut self) -> RxpolW<CfgSpec> {
1153        RxpolW::new(self, 22)
1154    }
1155    #[doc = "Bit 23 - Transmit data polarity."]
1156    #[inline(always)]
1157    pub fn txpol(&mut self) -> TxpolW<CfgSpec> {
1158        TxpolW::new(self, 23)
1159    }
1160}
1161#[doc = "USART Configuration register. Basic USART configuration settings that typically are not changed during operation.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1162pub struct CfgSpec;
1163impl crate::RegisterSpec for CfgSpec {
1164    type Ux = u32;
1165}
1166#[doc = "`read()` method returns [`cfg::R`](R) reader structure"]
1167impl crate::Readable for CfgSpec {}
1168#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
1169impl crate::Writable for CfgSpec {
1170    type Safety = crate::Unsafe;
1171    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1172    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1173}
1174#[doc = "`reset()` method sets CFG to value 0"]
1175impl crate::Resettable for CfgSpec {
1176    const RESET_VALUE: u32 = 0;
1177}
mimxrt685s_pac/usart0/cfg.rs

mimxrt685s_pac/usart0/
cfg.rs
