1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 _reserved0: [u8; 0x0400],
6 cfg: Cfg,
7 dly: Dly,
8 stat: Stat,
9 intenset: Intenset,
10 intenclr: Intenclr,
11 _reserved5: [u8; 0x10],
12 div: Div,
13 intstat: Intstat,
14 _reserved7: [u8; 0x09d4],
15 fifocfg: Fifocfg,
16 fifostat: Fifostat,
17 fifotrig: Fifotrig,
18 _reserved10: [u8; 0x04],
19 fifointenset: Fifointenset,
20 fifointenclr: Fifointenclr,
21 fifointstat: Fifointstat,
22 _reserved13: [u8; 0x04],
23 fifowr: Fifowr,
24 _reserved14: [u8; 0x0c],
25 fiford: Fiford,
26 _reserved15: [u8; 0x0c],
27 fifordnopop: Fifordnopop,
28 _reserved16: [u8; 0x04],
29 fifosize: Fifosize,
30 _reserved17: [u8; 0x01b0],
31 id: Id,
32}
33impl RegisterBlock {
34 #[doc = "0x400 - SPI Configuration register"]
35 #[inline(always)]
36 pub const fn cfg(&self) -> &Cfg {
37 &self.cfg
38 }
39 #[doc = "0x404 - SPI Delay register"]
40 #[inline(always)]
41 pub const fn dly(&self) -> &Dly {
42 &self.dly
43 }
44 #[doc = "0x408 - SPI Status. Some status flags can be cleared by writing a 1 to that bit position."]
45 #[inline(always)]
46 pub const fn stat(&self) -> &Stat {
47 &self.stat
48 }
49 #[doc = "0x40c - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."]
50 #[inline(always)]
51 pub const fn intenset(&self) -> &Intenset {
52 &self.intenset
53 }
54 #[doc = "0x410 - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."]
55 #[inline(always)]
56 pub const fn intenclr(&self) -> &Intenclr {
57 &self.intenclr
58 }
59 #[doc = "0x424 - SPI clock Divider"]
60 #[inline(always)]
61 pub const fn div(&self) -> &Div {
62 &self.div
63 }
64 #[doc = "0x428 - SPI Interrupt Status"]
65 #[inline(always)]
66 pub const fn intstat(&self) -> &Intstat {
67 &self.intstat
68 }
69 #[doc = "0xe00 - FIFO configuration and enable register."]
70 #[inline(always)]
71 pub const fn fifocfg(&self) -> &Fifocfg {
72 &self.fifocfg
73 }
74 #[doc = "0xe04 - FIFO status register."]
75 #[inline(always)]
76 pub const fn fifostat(&self) -> &Fifostat {
77 &self.fifostat
78 }
79 #[doc = "0xe08 - FIFO trigger settings for interrupt and DMA request."]
80 #[inline(always)]
81 pub const fn fifotrig(&self) -> &Fifotrig {
82 &self.fifotrig
83 }
84 #[doc = "0xe10 - FIFO interrupt enable set (enable) and read register."]
85 #[inline(always)]
86 pub const fn fifointenset(&self) -> &Fifointenset {
87 &self.fifointenset
88 }
89 #[doc = "0xe14 - FIFO interrupt enable clear (disable) and read register."]
90 #[inline(always)]
91 pub const fn fifointenclr(&self) -> &Fifointenclr {
92 &self.fifointenclr
93 }
94 #[doc = "0xe18 - FIFO interrupt status register."]
95 #[inline(always)]
96 pub const fn fifointstat(&self) -> &Fifointstat {
97 &self.fifointstat
98 }
99 #[doc = "0xe20 - FIFO write data."]
100 #[inline(always)]
101 pub const fn fifowr(&self) -> &Fifowr {
102 &self.fifowr
103 }
104 #[doc = "0xe30 - FIFO read data."]
105 #[inline(always)]
106 pub const fn fiford(&self) -> &Fiford {
107 &self.fiford
108 }
109 #[doc = "0xe40 - FIFO data read with no FIFO pop."]
110 #[inline(always)]
111 pub const fn fifordnopop(&self) -> &Fifordnopop {
112 &self.fifordnopop
113 }
114 #[doc = "0xe48 - FIFO size register"]
115 #[inline(always)]
116 pub const fn fifosize(&self) -> &Fifosize {
117 &self.fifosize
118 }
119 #[doc = "0xffc - Peripheral identification register."]
120 #[inline(always)]
121 pub const fn id(&self) -> &Id {
122 &self.id
123 }
124}
125#[doc = "CFG (rw) register accessor: SPI Configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`]
126module"]
127#[doc(alias = "CFG")]
128pub type Cfg = crate::Reg<cfg::CfgSpec>;
129#[doc = "SPI Configuration register"]
130pub mod cfg;
131#[doc = "DLY (rw) register accessor: SPI Delay register\n\nYou can [`read`](crate::Reg::read) this register and get [`dly::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dly::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dly`]
132module"]
133#[doc(alias = "DLY")]
134pub type Dly = crate::Reg<dly::DlySpec>;
135#[doc = "SPI Delay register"]
136pub mod dly;
137#[doc = "STAT (rw) register accessor: SPI Status. Some status flags can be cleared by writing a 1 to that bit position.\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
138module"]
139#[doc(alias = "STAT")]
140pub type Stat = crate::Reg<stat::StatSpec>;
141#[doc = "SPI Status. Some status flags can be cleared by writing a 1 to that bit position."]
142pub mod stat;
143#[doc = "INTENSET (rw) register accessor: SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenset`]
144module"]
145#[doc(alias = "INTENSET")]
146pub type Intenset = crate::Reg<intenset::IntensetSpec>;
147#[doc = "SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set."]
148pub mod intenset;
149#[doc = "INTENCLR (rw) register accessor: SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenclr`]
150module"]
151#[doc(alias = "INTENCLR")]
152pub type Intenclr = crate::Reg<intenclr::IntenclrSpec>;
153#[doc = "SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared."]
154pub mod intenclr;
155#[doc = "DIV (rw) register accessor: SPI clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`]
156module"]
157#[doc(alias = "DIV")]
158pub type Div = crate::Reg<div::DivSpec>;
159#[doc = "SPI clock Divider"]
160pub mod div;
161#[doc = "INTSTAT (r) register accessor: SPI Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstat`]
162module"]
163#[doc(alias = "INTSTAT")]
164pub type Intstat = crate::Reg<intstat::IntstatSpec>;
165#[doc = "SPI Interrupt Status"]
166pub mod intstat;
167#[doc = "FIFOCFG (rw) register accessor: FIFO configuration and enable register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifocfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifocfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifocfg`]
168module"]
169#[doc(alias = "FIFOCFG")]
170pub type Fifocfg = crate::Reg<fifocfg::FifocfgSpec>;
171#[doc = "FIFO configuration and enable register."]
172pub mod fifocfg;
173#[doc = "FIFOSTAT (rw) register accessor: FIFO status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifostat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifostat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifostat`]
174module"]
175#[doc(alias = "FIFOSTAT")]
176pub type Fifostat = crate::Reg<fifostat::FifostatSpec>;
177#[doc = "FIFO status register."]
178pub mod fifostat;
179#[doc = "FIFOTRIG (rw) register accessor: FIFO trigger settings for interrupt and DMA request.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifotrig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifotrig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifotrig`]
180module"]
181#[doc(alias = "FIFOTRIG")]
182pub type Fifotrig = crate::Reg<fifotrig::FifotrigSpec>;
183#[doc = "FIFO trigger settings for interrupt and DMA request."]
184pub mod fifotrig;
185#[doc = "FIFOINTENSET (rw) register accessor: FIFO interrupt enable set (enable) and read register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifointenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifointenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifointenset`]
186module"]
187#[doc(alias = "FIFOINTENSET")]
188pub type Fifointenset = crate::Reg<fifointenset::FifointensetSpec>;
189#[doc = "FIFO interrupt enable set (enable) and read register."]
190pub mod fifointenset;
191#[doc = "FIFOINTENCLR (rw) register accessor: FIFO interrupt enable clear (disable) and read register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifointenclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifointenclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifointenclr`]
192module"]
193#[doc(alias = "FIFOINTENCLR")]
194pub type Fifointenclr = crate::Reg<fifointenclr::FifointenclrSpec>;
195#[doc = "FIFO interrupt enable clear (disable) and read register."]
196pub mod fifointenclr;
197#[doc = "FIFOINTSTAT (r) register accessor: FIFO interrupt status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifointstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifointstat`]
198module"]
199#[doc(alias = "FIFOINTSTAT")]
200pub type Fifointstat = crate::Reg<fifointstat::FifointstatSpec>;
201#[doc = "FIFO interrupt status register."]
202pub mod fifointstat;
203#[doc = "FIFOWR (w) register accessor: FIFO write data.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifowr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifowr`]
204module"]
205#[doc(alias = "FIFOWR")]
206pub type Fifowr = crate::Reg<fifowr::FifowrSpec>;
207#[doc = "FIFO write data."]
208pub mod fifowr;
209#[doc = "FIFORD (r) register accessor: FIFO read data.\n\nYou can [`read`](crate::Reg::read) this register and get [`fiford::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fiford`]
210module"]
211#[doc(alias = "FIFORD")]
212pub type Fiford = crate::Reg<fiford::FifordSpec>;
213#[doc = "FIFO read data."]
214pub mod fiford;
215#[doc = "FIFORDNOPOP (r) register accessor: FIFO data read with no FIFO pop.\n\nYou can [`read`](crate::Reg::read) this register and get [`fifordnopop::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifordnopop`]
216module"]
217#[doc(alias = "FIFORDNOPOP")]
218pub type Fifordnopop = crate::Reg<fifordnopop::FifordnopopSpec>;
219#[doc = "FIFO data read with no FIFO pop."]
220pub mod fifordnopop;
221#[doc = "FIFOSIZE (rw) register accessor: FIFO size register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifosize::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifosize::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifosize`]
222module"]
223#[doc(alias = "FIFOSIZE")]
224pub type Fifosize = crate::Reg<fifosize::FifosizeSpec>;
225#[doc = "FIFO size register"]
226pub mod fifosize;
227#[doc = "ID (r) register accessor: Peripheral identification register.\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`]
228module"]
229#[doc(alias = "ID")]
230pub type Id = crate::Reg<id::IdSpec>;
231#[doc = "Peripheral identification register."]
232pub mod id;