mimxrt685s_pac/ocotp/
otp_clk_div.rs

1#[doc = "Register `OTP_CLK_DIV` reader"]
2pub type R = crate::R<OtpClkDivSpec>;
3#[doc = "Register `OTP_CLK_DIV` writer"]
4pub type W = crate::W<OtpClkDivSpec>;
5#[doc = "Clock divider value by -1 encoding. It's used to generate the clock to OTP memory (otp_clk) with apb_clk. The maximum otp_clk frequency is 120Mhz. 0: Divide by 1\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Div {
10    #[doc = "0: Divide by 1"]
11    Div1 = 0,
12    #[doc = "1: Divide by 2"]
13    Div2 = 1,
14    #[doc = "2: Divide by 3"]
15    Div3 = 2,
16    #[doc = "3: Divide by 4"]
17    Div4 = 3,
18    #[doc = "4: Divide by 5"]
19    Div5 = 4,
20    #[doc = "5: Divide by 6"]
21    Div6 = 5,
22    #[doc = "6: Divide by 7"]
23    Div7 = 6,
24    #[doc = "7: Divide by 8"]
25    Div8 = 7,
26    #[doc = "8: Divide by 9"]
27    Div9 = 8,
28    #[doc = "9: Divide by 10"]
29    Div10 = 9,
30    #[doc = "10: Divide by 11"]
31    Div11 = 10,
32    #[doc = "11: Divide by 12"]
33    Div12 = 11,
34    #[doc = "12: Divide by 13"]
35    Div13 = 12,
36    #[doc = "13: Divide by 14"]
37    Div14 = 13,
38    #[doc = "14: Divide by 15"]
39    Div15 = 14,
40    #[doc = "15: Divide by 16"]
41    Div16 = 15,
42}
43impl From<Div> for u8 {
44    #[inline(always)]
45    fn from(variant: Div) -> Self {
46        variant as _
47    }
48}
49impl crate::FieldSpec for Div {
50    type Ux = u8;
51}
52impl crate::IsEnum for Div {}
53#[doc = "Field `DIV` reader - Clock divider value by -1 encoding. It's used to generate the clock to OTP memory (otp_clk) with apb_clk. The maximum otp_clk frequency is 120Mhz. 0: Divide by 1"]
54pub type DivR = crate::FieldReader<Div>;
55impl DivR {
56    #[doc = "Get enumerated values variant"]
57    #[inline(always)]
58    pub const fn variant(&self) -> Div {
59        match self.bits {
60            0 => Div::Div1,
61            1 => Div::Div2,
62            2 => Div::Div3,
63            3 => Div::Div4,
64            4 => Div::Div5,
65            5 => Div::Div6,
66            6 => Div::Div7,
67            7 => Div::Div8,
68            8 => Div::Div9,
69            9 => Div::Div10,
70            10 => Div::Div11,
71            11 => Div::Div12,
72            12 => Div::Div13,
73            13 => Div::Div14,
74            14 => Div::Div15,
75            15 => Div::Div16,
76            _ => unreachable!(),
77        }
78    }
79    #[doc = "Divide by 1"]
80    #[inline(always)]
81    pub fn is_div_1(&self) -> bool {
82        *self == Div::Div1
83    }
84    #[doc = "Divide by 2"]
85    #[inline(always)]
86    pub fn is_div_2(&self) -> bool {
87        *self == Div::Div2
88    }
89    #[doc = "Divide by 3"]
90    #[inline(always)]
91    pub fn is_div_3(&self) -> bool {
92        *self == Div::Div3
93    }
94    #[doc = "Divide by 4"]
95    #[inline(always)]
96    pub fn is_div_4(&self) -> bool {
97        *self == Div::Div4
98    }
99    #[doc = "Divide by 5"]
100    #[inline(always)]
101    pub fn is_div_5(&self) -> bool {
102        *self == Div::Div5
103    }
104    #[doc = "Divide by 6"]
105    #[inline(always)]
106    pub fn is_div_6(&self) -> bool {
107        *self == Div::Div6
108    }
109    #[doc = "Divide by 7"]
110    #[inline(always)]
111    pub fn is_div_7(&self) -> bool {
112        *self == Div::Div7
113    }
114    #[doc = "Divide by 8"]
115    #[inline(always)]
116    pub fn is_div_8(&self) -> bool {
117        *self == Div::Div8
118    }
119    #[doc = "Divide by 9"]
120    #[inline(always)]
121    pub fn is_div_9(&self) -> bool {
122        *self == Div::Div9
123    }
124    #[doc = "Divide by 10"]
125    #[inline(always)]
126    pub fn is_div_10(&self) -> bool {
127        *self == Div::Div10
128    }
129    #[doc = "Divide by 11"]
130    #[inline(always)]
131    pub fn is_div_11(&self) -> bool {
132        *self == Div::Div11
133    }
134    #[doc = "Divide by 12"]
135    #[inline(always)]
136    pub fn is_div_12(&self) -> bool {
137        *self == Div::Div12
138    }
139    #[doc = "Divide by 13"]
140    #[inline(always)]
141    pub fn is_div_13(&self) -> bool {
142        *self == Div::Div13
143    }
144    #[doc = "Divide by 14"]
145    #[inline(always)]
146    pub fn is_div_14(&self) -> bool {
147        *self == Div::Div14
148    }
149    #[doc = "Divide by 15"]
150    #[inline(always)]
151    pub fn is_div_15(&self) -> bool {
152        *self == Div::Div15
153    }
154    #[doc = "Divide by 16"]
155    #[inline(always)]
156    pub fn is_div_16(&self) -> bool {
157        *self == Div::Div16
158    }
159}
160#[doc = "Field `DIV` writer - Clock divider value by -1 encoding. It's used to generate the clock to OTP memory (otp_clk) with apb_clk. The maximum otp_clk frequency is 120Mhz. 0: Divide by 1"]
161pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4, Div, crate::Safe>;
162impl<'a, REG> DivW<'a, REG>
163where
164    REG: crate::Writable + crate::RegisterSpec,
165    REG::Ux: From<u8>,
166{
167    #[doc = "Divide by 1"]
168    #[inline(always)]
169    pub fn div_1(self) -> &'a mut crate::W<REG> {
170        self.variant(Div::Div1)
171    }
172    #[doc = "Divide by 2"]
173    #[inline(always)]
174    pub fn div_2(self) -> &'a mut crate::W<REG> {
175        self.variant(Div::Div2)
176    }
177    #[doc = "Divide by 3"]
178    #[inline(always)]
179    pub fn div_3(self) -> &'a mut crate::W<REG> {
180        self.variant(Div::Div3)
181    }
182    #[doc = "Divide by 4"]
183    #[inline(always)]
184    pub fn div_4(self) -> &'a mut crate::W<REG> {
185        self.variant(Div::Div4)
186    }
187    #[doc = "Divide by 5"]
188    #[inline(always)]
189    pub fn div_5(self) -> &'a mut crate::W<REG> {
190        self.variant(Div::Div5)
191    }
192    #[doc = "Divide by 6"]
193    #[inline(always)]
194    pub fn div_6(self) -> &'a mut crate::W<REG> {
195        self.variant(Div::Div6)
196    }
197    #[doc = "Divide by 7"]
198    #[inline(always)]
199    pub fn div_7(self) -> &'a mut crate::W<REG> {
200        self.variant(Div::Div7)
201    }
202    #[doc = "Divide by 8"]
203    #[inline(always)]
204    pub fn div_8(self) -> &'a mut crate::W<REG> {
205        self.variant(Div::Div8)
206    }
207    #[doc = "Divide by 9"]
208    #[inline(always)]
209    pub fn div_9(self) -> &'a mut crate::W<REG> {
210        self.variant(Div::Div9)
211    }
212    #[doc = "Divide by 10"]
213    #[inline(always)]
214    pub fn div_10(self) -> &'a mut crate::W<REG> {
215        self.variant(Div::Div10)
216    }
217    #[doc = "Divide by 11"]
218    #[inline(always)]
219    pub fn div_11(self) -> &'a mut crate::W<REG> {
220        self.variant(Div::Div11)
221    }
222    #[doc = "Divide by 12"]
223    #[inline(always)]
224    pub fn div_12(self) -> &'a mut crate::W<REG> {
225        self.variant(Div::Div12)
226    }
227    #[doc = "Divide by 13"]
228    #[inline(always)]
229    pub fn div_13(self) -> &'a mut crate::W<REG> {
230        self.variant(Div::Div13)
231    }
232    #[doc = "Divide by 14"]
233    #[inline(always)]
234    pub fn div_14(self) -> &'a mut crate::W<REG> {
235        self.variant(Div::Div14)
236    }
237    #[doc = "Divide by 15"]
238    #[inline(always)]
239    pub fn div_15(self) -> &'a mut crate::W<REG> {
240        self.variant(Div::Div15)
241    }
242    #[doc = "Divide by 16"]
243    #[inline(always)]
244    pub fn div_16(self) -> &'a mut crate::W<REG> {
245        self.variant(Div::Div16)
246    }
247}
248#[doc = "Field `RESET` reader - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count."]
249pub type ResetR = crate::BitReader;
250#[doc = "Field `RESET` writer - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count."]
251pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>;
252#[doc = "Field `HALT` reader - Halts the divider counter. The intent is to allow the divider's clock source to be changed without the risk of a glitch at the output."]
253pub type HaltR = crate::BitReader;
254#[doc = "Field `HALT` writer - Halts the divider counter. The intent is to allow the divider's clock source to be changed without the risk of a glitch at the output."]
255pub type HaltW<'a, REG> = crate::BitWriter<'a, REG>;
256#[doc = "Field `REQFLAG` reader - Divider status flag. Set when a change is made to the divider value, cleared when the change is complete."]
257pub type ReqflagR = crate::BitReader;
258impl R {
259    #[doc = "Bits 0:3 - Clock divider value by -1 encoding. It's used to generate the clock to OTP memory (otp_clk) with apb_clk. The maximum otp_clk frequency is 120Mhz. 0: Divide by 1"]
260    #[inline(always)]
261    pub fn div(&self) -> DivR {
262        DivR::new((self.bits & 0x0f) as u8)
263    }
264    #[doc = "Bit 29 - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count."]
265    #[inline(always)]
266    pub fn reset(&self) -> ResetR {
267        ResetR::new(((self.bits >> 29) & 1) != 0)
268    }
269    #[doc = "Bit 30 - Halts the divider counter. The intent is to allow the divider's clock source to be changed without the risk of a glitch at the output."]
270    #[inline(always)]
271    pub fn halt(&self) -> HaltR {
272        HaltR::new(((self.bits >> 30) & 1) != 0)
273    }
274    #[doc = "Bit 31 - Divider status flag. Set when a change is made to the divider value, cleared when the change is complete."]
275    #[inline(always)]
276    pub fn reqflag(&self) -> ReqflagR {
277        ReqflagR::new(((self.bits >> 31) & 1) != 0)
278    }
279}
280#[cfg(feature = "debug")]
281impl core::fmt::Debug for R {
282    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
283        f.debug_struct("OTP_CLK_DIV")
284            .field("div", &self.div())
285            .field("reset", &self.reset())
286            .field("halt", &self.halt())
287            .field("reqflag", &self.reqflag())
288            .finish()
289    }
290}
291impl W {
292    #[doc = "Bits 0:3 - Clock divider value by -1 encoding. It's used to generate the clock to OTP memory (otp_clk) with apb_clk. The maximum otp_clk frequency is 120Mhz. 0: Divide by 1"]
293    #[inline(always)]
294    pub fn div(&mut self) -> DivW<OtpClkDivSpec> {
295        DivW::new(self, 0)
296    }
297    #[doc = "Bit 29 - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count."]
298    #[inline(always)]
299    pub fn reset(&mut self) -> ResetW<OtpClkDivSpec> {
300        ResetW::new(self, 29)
301    }
302    #[doc = "Bit 30 - Halts the divider counter. The intent is to allow the divider's clock source to be changed without the risk of a glitch at the output."]
303    #[inline(always)]
304    pub fn halt(&mut self) -> HaltW<OtpClkDivSpec> {
305        HaltW::new(self, 30)
306    }
307}
308#[doc = "OTP clock divider register\n\nYou can [`read`](crate::Reg::read) this register and get [`otp_clk_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otp_clk_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
309pub struct OtpClkDivSpec;
310impl crate::RegisterSpec for OtpClkDivSpec {
311    type Ux = u32;
312}
313#[doc = "`read()` method returns [`otp_clk_div::R`](R) reader structure"]
314impl crate::Readable for OtpClkDivSpec {}
315#[doc = "`write(|w| ..)` method takes [`otp_clk_div::W`](W) writer structure"]
316impl crate::Writable for OtpClkDivSpec {
317    type Safety = crate::Unsafe;
318    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
319    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
320}
321#[doc = "`reset()` method sets OTP_CLK_DIV to value 0"]
322impl crate::Resettable for OtpClkDivSpec {
323    const RESET_VALUE: u32 = 0;
324}
mimxrt685s_pac/ocotp/otp_clk_div.rs

mimxrt685s_pac/ocotp/
otp_clk_div.rs
