1#[doc = "Register `MSTCTL` reader"]
2pub type R = crate::R<MstctlSpec>;
3#[doc = "Register `MSTCTL` writer"]
4pub type W = crate::W<MstctlSpec>;
5#[doc = "Master Continue. This bit is write-only.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Mstcontinue {
9 #[doc = "0: No effect."]
10 NoEffect = 0,
11 #[doc = "1: Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation."]
12 Continue = 1,
13}
14impl From<Mstcontinue> for bool {
15 #[inline(always)]
16 fn from(variant: Mstcontinue) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `MSTCONTINUE` writer - Master Continue. This bit is write-only."]
21pub type MstcontinueW<'a, REG> = crate::BitWriter<'a, REG, Mstcontinue>;
22impl<'a, REG> MstcontinueW<'a, REG>
23where
24 REG: crate::Writable + crate::RegisterSpec,
25{
26 #[doc = "No effect."]
27 #[inline(always)]
28 pub fn no_effect(self) -> &'a mut crate::W<REG> {
29 self.variant(Mstcontinue::NoEffect)
30 }
31 #[doc = "Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation."]
32 #[inline(always)]
33 pub fn continue_(self) -> &'a mut crate::W<REG> {
34 self.variant(Mstcontinue::Continue)
35 }
36}
37#[doc = "Master Start control. This bit is write-only.\n\nValue on reset: 0"]
38#[cfg_attr(feature = "defmt", derive(defmt::Format))]
39#[derive(Clone, Copy, Debug, PartialEq, Eq)]
40pub enum Mststart {
41 #[doc = "0: No effect."]
42 NoEffect = 0,
43 #[doc = "1: Start. A Start will be generated on the I2C bus at the next allowed time."]
44 Start = 1,
45}
46impl From<Mststart> for bool {
47 #[inline(always)]
48 fn from(variant: Mststart) -> Self {
49 variant as u8 != 0
50 }
51}
52#[doc = "Field `MSTSTART` reader - Master Start control. This bit is write-only."]
53pub type MststartR = crate::BitReader<Mststart>;
54impl MststartR {
55 #[doc = "Get enumerated values variant"]
56 #[inline(always)]
57 pub const fn variant(&self) -> Mststart {
58 match self.bits {
59 false => Mststart::NoEffect,
60 true => Mststart::Start,
61 }
62 }
63 #[doc = "No effect."]
64 #[inline(always)]
65 pub fn is_no_effect(&self) -> bool {
66 *self == Mststart::NoEffect
67 }
68 #[doc = "Start. A Start will be generated on the I2C bus at the next allowed time."]
69 #[inline(always)]
70 pub fn is_start(&self) -> bool {
71 *self == Mststart::Start
72 }
73}
74#[doc = "Field `MSTSTART` writer - Master Start control. This bit is write-only."]
75pub type MststartW<'a, REG> = crate::BitWriter<'a, REG, Mststart>;
76impl<'a, REG> MststartW<'a, REG>
77where
78 REG: crate::Writable + crate::RegisterSpec,
79{
80 #[doc = "No effect."]
81 #[inline(always)]
82 pub fn no_effect(self) -> &'a mut crate::W<REG> {
83 self.variant(Mststart::NoEffect)
84 }
85 #[doc = "Start. A Start will be generated on the I2C bus at the next allowed time."]
86 #[inline(always)]
87 pub fn start(self) -> &'a mut crate::W<REG> {
88 self.variant(Mststart::Start)
89 }
90}
91#[doc = "Master Stop control. This bit is write-only.\n\nValue on reset: 0"]
92#[cfg_attr(feature = "defmt", derive(defmt::Format))]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94pub enum Mststop {
95 #[doc = "0: No effect."]
96 NoEffect = 0,
97 #[doc = "1: Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode)."]
98 Stop = 1,
99}
100impl From<Mststop> for bool {
101 #[inline(always)]
102 fn from(variant: Mststop) -> Self {
103 variant as u8 != 0
104 }
105}
106#[doc = "Field `MSTSTOP` reader - Master Stop control. This bit is write-only."]
107pub type MststopR = crate::BitReader<Mststop>;
108impl MststopR {
109 #[doc = "Get enumerated values variant"]
110 #[inline(always)]
111 pub const fn variant(&self) -> Mststop {
112 match self.bits {
113 false => Mststop::NoEffect,
114 true => Mststop::Stop,
115 }
116 }
117 #[doc = "No effect."]
118 #[inline(always)]
119 pub fn is_no_effect(&self) -> bool {
120 *self == Mststop::NoEffect
121 }
122 #[doc = "Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode)."]
123 #[inline(always)]
124 pub fn is_stop(&self) -> bool {
125 *self == Mststop::Stop
126 }
127}
128#[doc = "Field `MSTSTOP` writer - Master Stop control. This bit is write-only."]
129pub type MststopW<'a, REG> = crate::BitWriter<'a, REG, Mststop>;
130impl<'a, REG> MststopW<'a, REG>
131where
132 REG: crate::Writable + crate::RegisterSpec,
133{
134 #[doc = "No effect."]
135 #[inline(always)]
136 pub fn no_effect(self) -> &'a mut crate::W<REG> {
137 self.variant(Mststop::NoEffect)
138 }
139 #[doc = "Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode)."]
140 #[inline(always)]
141 pub fn stop(self) -> &'a mut crate::W<REG> {
142 self.variant(Mststop::Stop)
143 }
144}
145#[doc = "Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.\n\nValue on reset: 0"]
146#[cfg_attr(feature = "defmt", derive(defmt::Format))]
147#[derive(Clone, Copy, Debug, PartialEq, Eq)]
148pub enum Mstdma {
149 #[doc = "0: Disable. No DMA requests are generated for master operation."]
150 Disabled = 0,
151 #[doc = "1: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically."]
152 Enabled = 1,
153}
154impl From<Mstdma> for bool {
155 #[inline(always)]
156 fn from(variant: Mstdma) -> Self {
157 variant as u8 != 0
158 }
159}
160#[doc = "Field `MSTDMA` reader - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write."]
161pub type MstdmaR = crate::BitReader<Mstdma>;
162impl MstdmaR {
163 #[doc = "Get enumerated values variant"]
164 #[inline(always)]
165 pub const fn variant(&self) -> Mstdma {
166 match self.bits {
167 false => Mstdma::Disabled,
168 true => Mstdma::Enabled,
169 }
170 }
171 #[doc = "Disable. No DMA requests are generated for master operation."]
172 #[inline(always)]
173 pub fn is_disabled(&self) -> bool {
174 *self == Mstdma::Disabled
175 }
176 #[doc = "Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically."]
177 #[inline(always)]
178 pub fn is_enabled(&self) -> bool {
179 *self == Mstdma::Enabled
180 }
181}
182#[doc = "Field `MSTDMA` writer - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write."]
183pub type MstdmaW<'a, REG> = crate::BitWriter<'a, REG, Mstdma>;
184impl<'a, REG> MstdmaW<'a, REG>
185where
186 REG: crate::Writable + crate::RegisterSpec,
187{
188 #[doc = "Disable. No DMA requests are generated for master operation."]
189 #[inline(always)]
190 pub fn disabled(self) -> &'a mut crate::W<REG> {
191 self.variant(Mstdma::Disabled)
192 }
193 #[doc = "Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically."]
194 #[inline(always)]
195 pub fn enabled(self) -> &'a mut crate::W<REG> {
196 self.variant(Mstdma::Enabled)
197 }
198}
199impl R {
200 #[doc = "Bit 1 - Master Start control. This bit is write-only."]
201 #[inline(always)]
202 pub fn mststart(&self) -> MststartR {
203 MststartR::new(((self.bits >> 1) & 1) != 0)
204 }
205 #[doc = "Bit 2 - Master Stop control. This bit is write-only."]
206 #[inline(always)]
207 pub fn mststop(&self) -> MststopR {
208 MststopR::new(((self.bits >> 2) & 1) != 0)
209 }
210 #[doc = "Bit 3 - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write."]
211 #[inline(always)]
212 pub fn mstdma(&self) -> MstdmaR {
213 MstdmaR::new(((self.bits >> 3) & 1) != 0)
214 }
215}
216#[cfg(feature = "debug")]
217impl core::fmt::Debug for R {
218 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
219 f.debug_struct("MSTCTL")
220 .field("mststart", &self.mststart())
221 .field("mststop", &self.mststop())
222 .field("mstdma", &self.mstdma())
223 .finish()
224 }
225}
226impl W {
227 #[doc = "Bit 0 - Master Continue. This bit is write-only."]
228 #[inline(always)]
229 pub fn mstcontinue(&mut self) -> MstcontinueW<MstctlSpec> {
230 MstcontinueW::new(self, 0)
231 }
232 #[doc = "Bit 1 - Master Start control. This bit is write-only."]
233 #[inline(always)]
234 pub fn mststart(&mut self) -> MststartW<MstctlSpec> {
235 MststartW::new(self, 1)
236 }
237 #[doc = "Bit 2 - Master Stop control. This bit is write-only."]
238 #[inline(always)]
239 pub fn mststop(&mut self) -> MststopW<MstctlSpec> {
240 MststopW::new(self, 2)
241 }
242 #[doc = "Bit 3 - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write."]
243 #[inline(always)]
244 pub fn mstdma(&mut self) -> MstdmaW<MstctlSpec> {
245 MstdmaW::new(self, 3)
246 }
247}
248#[doc = "Master control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mstctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mstctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
249pub struct MstctlSpec;
250impl crate::RegisterSpec for MstctlSpec {
251 type Ux = u32;
252}
253#[doc = "`read()` method returns [`mstctl::R`](R) reader structure"]
254impl crate::Readable for MstctlSpec {}
255#[doc = "`write(|w| ..)` method takes [`mstctl::W`](W) writer structure"]
256impl crate::Writable for MstctlSpec {
257 type Safety = crate::Unsafe;
258 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
259 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
260}
261#[doc = "`reset()` method sets MSTCTL to value 0"]
262impl crate::Resettable for MstctlSpec {
263 const RESET_VALUE: u32 = 0;
264}