mimxrt685s_pac/dma0/
busy1.rs

1#[doc = "Register `BUSY1` reader"]
2pub type R = crate::R<Busy1Spec>;
3#[doc = "Busy flag for DMA channel 32.\n\nValue on reset: 0"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Busy32 {
7    #[doc = "0: DMAchannel 32 is not busy."]
8    NotBusy = 0,
9    #[doc = "1: DMAchannel 0 is busy."]
10    Busy = 1,
11}
12impl From<Busy32> for bool {
13    #[inline(always)]
14    fn from(variant: Busy32) -> Self {
15        variant as u8 != 0
16    }
17}
18#[doc = "Field `BUSY32` reader - Busy flag for DMA channel 32."]
19pub type Busy32R = crate::BitReader<Busy32>;
20impl Busy32R {
21    #[doc = "Get enumerated values variant"]
22    #[inline(always)]
23    pub const fn variant(&self) -> Busy32 {
24        match self.bits {
25            false => Busy32::NotBusy,
26            true => Busy32::Busy,
27        }
28    }
29    #[doc = "DMAchannel 32 is not busy."]
30    #[inline(always)]
31    pub fn is_not_busy(&self) -> bool {
32        *self == Busy32::NotBusy
33    }
34    #[doc = "DMAchannel 0 is busy."]
35    #[inline(always)]
36    pub fn is_busy(&self) -> bool {
37        *self == Busy32::Busy
38    }
39}
40#[doc = "Additional Active flags for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved.\n\nValue on reset: 0"]
41#[cfg_attr(feature = "defmt", derive(defmt::Format))]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u32)]
44pub enum Busy63_33 {
45    #[doc = "0: The relevant DMA channel is not busy."]
46    NotBusy = 0,
47    #[doc = "1: The relevant DMA channel is busy."]
48    Busy = 1,
49}
50impl From<Busy63_33> for u32 {
51    #[inline(always)]
52    fn from(variant: Busy63_33) -> Self {
53        variant as _
54    }
55}
56impl crate::FieldSpec for Busy63_33 {
57    type Ux = u32;
58}
59impl crate::IsEnum for Busy63_33 {}
60#[doc = "Field `BUSY63_33` reader - Additional Active flags for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved."]
61pub type Busy63_33R = crate::FieldReader<Busy63_33>;
62impl Busy63_33R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub const fn variant(&self) -> Option<Busy63_33> {
66        match self.bits {
67            0 => Some(Busy63_33::NotBusy),
68            1 => Some(Busy63_33::Busy),
69            _ => None,
70        }
71    }
72    #[doc = "The relevant DMA channel is not busy."]
73    #[inline(always)]
74    pub fn is_not_busy(&self) -> bool {
75        *self == Busy63_33::NotBusy
76    }
77    #[doc = "The relevant DMA channel is busy."]
78    #[inline(always)]
79    pub fn is_busy(&self) -> bool {
80        *self == Busy63_33::Busy
81    }
82}
83impl R {
84    #[doc = "Bit 0 - Busy flag for DMA channel 32."]
85    #[inline(always)]
86    pub fn busy32(&self) -> Busy32R {
87        Busy32R::new((self.bits & 1) != 0)
88    }
89    #[doc = "Bits 1:31 - Additional Active flags for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved."]
90    #[inline(always)]
91    pub fn busy63_33(&self) -> Busy63_33R {
92        Busy63_33R::new((self.bits >> 1) & 0x7fff_ffff)
93    }
94}
95#[cfg(feature = "debug")]
96impl core::fmt::Debug for R {
97    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
98        f.debug_struct("BUSY1")
99            .field("busy32", &self.busy32())
100            .field("busy63_33", &self.busy63_33())
101            .finish()
102    }
103}
104#[doc = "Channel Busy status for all DMA channels.\n\nYou can [`read`](crate::Reg::read) this register and get [`busy1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
105pub struct Busy1Spec;
106impl crate::RegisterSpec for Busy1Spec {
107    type Ux = u32;
108}
109#[doc = "`read()` method returns [`busy1::R`](R) reader structure"]
110impl crate::Readable for Busy1Spec {}
111#[doc = "`reset()` method sets BUSY1 to value 0"]
112impl crate::Resettable for Busy1Spec {
113    const RESET_VALUE: u32 = 0;
114}
mimxrt685s_pac/dma0/busy1.rs

mimxrt685s_pac/dma0/
busy1.rs
