mimxrt685s_pac/clkctl0/
mainclkselb.rs

1#[doc = "Register `MAINCLKSELB` reader"]
2pub type R = crate::R<MainclkselbSpec>;
3#[doc = "Register `MAINCLKSELB` writer"]
4pub type W = crate::W<MainclkselbSpec>;
5#[doc = "Main Clock Source Selection. . .\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Sel {
10    #[doc = "0: MAINCLKSELA 1st Stage Clock."]
11    Main1stClk = 0,
12    #[doc = "1: SFRO Clock."]
13    SfroClk = 1,
14    #[doc = "2: Main System PLL Clock."]
15    MainPllClk = 2,
16    #[doc = "3: RTC 32KHz Clock."]
17    Rtc32kClk = 3,
18}
19impl From<Sel> for u8 {
20    #[inline(always)]
21    fn from(variant: Sel) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for Sel {
26    type Ux = u8;
27}
28impl crate::IsEnum for Sel {}
29#[doc = "Field `SEL` reader - Main Clock Source Selection. . ."]
30pub type SelR = crate::FieldReader<Sel>;
31impl SelR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> Sel {
35        match self.bits {
36            0 => Sel::Main1stClk,
37            1 => Sel::SfroClk,
38            2 => Sel::MainPllClk,
39            3 => Sel::Rtc32kClk,
40            _ => unreachable!(),
41        }
42    }
43    #[doc = "MAINCLKSELA 1st Stage Clock."]
44    #[inline(always)]
45    pub fn is_main_1st_clk(&self) -> bool {
46        *self == Sel::Main1stClk
47    }
48    #[doc = "SFRO Clock."]
49    #[inline(always)]
50    pub fn is_sfro_clk(&self) -> bool {
51        *self == Sel::SfroClk
52    }
53    #[doc = "Main System PLL Clock."]
54    #[inline(always)]
55    pub fn is_main_pll_clk(&self) -> bool {
56        *self == Sel::MainPllClk
57    }
58    #[doc = "RTC 32KHz Clock."]
59    #[inline(always)]
60    pub fn is_rtc_32k_clk(&self) -> bool {
61        *self == Sel::Rtc32kClk
62    }
63}
64#[doc = "Field `SEL` writer - Main Clock Source Selection. . ."]
65pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sel, crate::Safe>;
66impl<'a, REG> SelW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "MAINCLKSELA 1st Stage Clock."]
72    #[inline(always)]
73    pub fn main_1st_clk(self) -> &'a mut crate::W<REG> {
74        self.variant(Sel::Main1stClk)
75    }
76    #[doc = "SFRO Clock."]
77    #[inline(always)]
78    pub fn sfro_clk(self) -> &'a mut crate::W<REG> {
79        self.variant(Sel::SfroClk)
80    }
81    #[doc = "Main System PLL Clock."]
82    #[inline(always)]
83    pub fn main_pll_clk(self) -> &'a mut crate::W<REG> {
84        self.variant(Sel::MainPllClk)
85    }
86    #[doc = "RTC 32KHz Clock."]
87    #[inline(always)]
88    pub fn rtc_32k_clk(self) -> &'a mut crate::W<REG> {
89        self.variant(Sel::Rtc32kClk)
90    }
91}
92impl R {
93    #[doc = "Bits 0:1 - Main Clock Source Selection. . ."]
94    #[inline(always)]
95    pub fn sel(&self) -> SelR {
96        SelR::new((self.bits & 3) as u8)
97    }
98}
99#[cfg(feature = "debug")]
100impl core::fmt::Debug for R {
101    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
102        f.debug_struct("MAINCLKSELB")
103            .field("sel", &self.sel())
104            .finish()
105    }
106}
107impl W {
108    #[doc = "Bits 0:1 - Main Clock Source Selection. . ."]
109    #[inline(always)]
110    pub fn sel(&mut self) -> SelW<MainclkselbSpec> {
111        SelW::new(self, 0)
112    }
113}
114#[doc = "main clock selection B\n\nYou can [`read`](crate::Reg::read) this register and get [`mainclkselb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mainclkselb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct MainclkselbSpec;
116impl crate::RegisterSpec for MainclkselbSpec {
117    type Ux = u32;
118}
119#[doc = "`read()` method returns [`mainclkselb::R`](R) reader structure"]
120impl crate::Readable for MainclkselbSpec {}
121#[doc = "`write(|w| ..)` method takes [`mainclkselb::W`](W) writer structure"]
122impl crate::Writable for MainclkselbSpec {
123    type Safety = crate::Unsafe;
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
126}
127#[doc = "`reset()` method sets MAINCLKSELB to value 0"]
128impl crate::Resettable for MainclkselbSpec {
129    const RESET_VALUE: u32 = 0;
130}
mimxrt685s_pac/clkctl0/mainclkselb.rs

mimxrt685s_pac/clkctl0/
mainclkselb.rs
