mimxrt685s_pac/clkctl0/
adc0fclksel0.rs

1#[doc = "Register `ADC0FCLKSEL0` reader"]
2pub type R = crate::R<Adc0fclksel0Spec>;
3#[doc = "Register `ADC0FCLKSEL0` writer"]
4pub type W = crate::W<Adc0fclksel0Spec>;
5#[doc = "Clock Output Select 1st Stage. . .\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Sel {
10    #[doc = "0: SFRO Clock."]
11    SfroClk = 0,
12    #[doc = "1: XTALIN Clock."]
13    XtalinClk = 1,
14    #[doc = "2: Low Power Oscillator Clock (LPOSC)."]
15    Lposc = 2,
16    #[doc = "3: FFRO Clock."]
17    FfroClk = 3,
18    #[doc = "7: None, this may be selected in order to reduce power when no output is needed."]
19    None = 7,
20}
21impl From<Sel> for u8 {
22    #[inline(always)]
23    fn from(variant: Sel) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for Sel {
28    type Ux = u8;
29}
30impl crate::IsEnum for Sel {}
31#[doc = "Field `SEL` reader - Clock Output Select 1st Stage. . ."]
32pub type SelR = crate::FieldReader<Sel>;
33impl SelR {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> Option<Sel> {
37        match self.bits {
38            0 => Some(Sel::SfroClk),
39            1 => Some(Sel::XtalinClk),
40            2 => Some(Sel::Lposc),
41            3 => Some(Sel::FfroClk),
42            7 => Some(Sel::None),
43            _ => None,
44        }
45    }
46    #[doc = "SFRO Clock."]
47    #[inline(always)]
48    pub fn is_sfro_clk(&self) -> bool {
49        *self == Sel::SfroClk
50    }
51    #[doc = "XTALIN Clock."]
52    #[inline(always)]
53    pub fn is_xtalin_clk(&self) -> bool {
54        *self == Sel::XtalinClk
55    }
56    #[doc = "Low Power Oscillator Clock (LPOSC)."]
57    #[inline(always)]
58    pub fn is_lposc(&self) -> bool {
59        *self == Sel::Lposc
60    }
61    #[doc = "FFRO Clock."]
62    #[inline(always)]
63    pub fn is_ffro_clk(&self) -> bool {
64        *self == Sel::FfroClk
65    }
66    #[doc = "None, this may be selected in order to reduce power when no output is needed."]
67    #[inline(always)]
68    pub fn is_none(&self) -> bool {
69        *self == Sel::None
70    }
71}
72#[doc = "Field `SEL` writer - Clock Output Select 1st Stage. . ."]
73pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sel>;
74impl<'a, REG> SelW<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77    REG::Ux: From<u8>,
78{
79    #[doc = "SFRO Clock."]
80    #[inline(always)]
81    pub fn sfro_clk(self) -> &'a mut crate::W<REG> {
82        self.variant(Sel::SfroClk)
83    }
84    #[doc = "XTALIN Clock."]
85    #[inline(always)]
86    pub fn xtalin_clk(self) -> &'a mut crate::W<REG> {
87        self.variant(Sel::XtalinClk)
88    }
89    #[doc = "Low Power Oscillator Clock (LPOSC)."]
90    #[inline(always)]
91    pub fn lposc(self) -> &'a mut crate::W<REG> {
92        self.variant(Sel::Lposc)
93    }
94    #[doc = "FFRO Clock."]
95    #[inline(always)]
96    pub fn ffro_clk(self) -> &'a mut crate::W<REG> {
97        self.variant(Sel::FfroClk)
98    }
99    #[doc = "None, this may be selected in order to reduce power when no output is needed."]
100    #[inline(always)]
101    pub fn none(self) -> &'a mut crate::W<REG> {
102        self.variant(Sel::None)
103    }
104}
105impl R {
106    #[doc = "Bits 0:2 - Clock Output Select 1st Stage. . ."]
107    #[inline(always)]
108    pub fn sel(&self) -> SelR {
109        SelR::new((self.bits & 7) as u8)
110    }
111}
112#[cfg(feature = "debug")]
113impl core::fmt::Debug for R {
114    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
115        f.debug_struct("ADC0FCLKSEL0")
116            .field("sel", &self.sel())
117            .finish()
118    }
119}
120impl W {
121    #[doc = "Bits 0:2 - Clock Output Select 1st Stage. . ."]
122    #[inline(always)]
123    pub fn sel(&mut self) -> SelW<Adc0fclksel0Spec> {
124        SelW::new(self, 0)
125    }
126}
127#[doc = "ADC0 fclk selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc0fclksel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc0fclksel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
128pub struct Adc0fclksel0Spec;
129impl crate::RegisterSpec for Adc0fclksel0Spec {
130    type Ux = u32;
131}
132#[doc = "`read()` method returns [`adc0fclksel0::R`](R) reader structure"]
133impl crate::Readable for Adc0fclksel0Spec {}
134#[doc = "`write(|w| ..)` method takes [`adc0fclksel0::W`](W) writer structure"]
135impl crate::Writable for Adc0fclksel0Spec {
136    type Safety = crate::Unsafe;
137    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
138    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
139}
140#[doc = "`reset()` method sets ADC0FCLKSEL0 to value 0x07"]
141impl crate::Resettable for Adc0fclksel0Spec {
142    const RESET_VALUE: u32 = 0x07;
143}
mimxrt685s_pac/clkctl0/adc0fclksel0.rs

mimxrt685s_pac/clkctl0/
adc0fclksel0.rs
