Crate mcxn947_pac

Expand description

Peripheral access API for MCXN947_CM33_CORE0 microcontrollers (generated using svd2rust v0.31.5 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use self::Interrupt as interrupt;
pub use self::ctimer0 as ctimer1;
pub use self::ctimer0 as ctimer2;
pub use self::ctimer0 as ctimer3;
pub use self::ctimer0 as ctimer4;
pub use self::wwdt0 as wwdt1;
pub use self::i3c0 as i3c1;
pub use self::gdet0 as gdet1;
pub use self::port0 as port5;
pub use self::lptmr0 as lptmr1;
pub use self::cmp0 as cmp1;
pub use self::cmp0 as cmp2;
pub use self::dma0 as dma1;
pub use self::lpspi0 as lpspi1;
pub use self::lpspi0 as lpspi2;
pub use self::lpspi0 as lpspi3;
pub use self::lpspi0 as lpspi4;
pub use self::lpspi0 as lpspi5;
pub use self::lpspi0 as lpspi6;
pub use self::lpspi0 as lpspi7;
pub use self::lpspi0 as lpspi8;
pub use self::lpspi0 as lpspi9;
pub use self::lpuart0 as lpuart1;
pub use self::lpuart0 as lpuart2;
pub use self::lpuart0 as lpuart3;
pub use self::lpuart0 as lpuart4;
pub use self::lpuart0 as lpuart5;
pub use self::lpuart0 as lpuart6;
pub use self::lpuart0 as lpuart7;
pub use self::lpuart0 as lpuart8;
pub use self::lpuart0 as lpuart9;
pub use self::lp_flexcomm0 as lp_flexcomm1;
pub use self::lp_flexcomm0 as lp_flexcomm2;
pub use self::lp_flexcomm0 as lp_flexcomm3;
pub use self::lp_flexcomm0 as lp_flexcomm4;
pub use self::lp_flexcomm0 as lp_flexcomm5;
pub use self::lp_flexcomm0 as lp_flexcomm6;
pub use self::lp_flexcomm0 as lp_flexcomm7;
pub use self::lp_flexcomm0 as lp_flexcomm8;
pub use self::lp_flexcomm0 as lp_flexcomm9;
pub use self::lpi2c0 as lpi2c1;
pub use self::lpi2c0 as lpi2c2;
pub use self::lpi2c0 as lpi2c3;
pub use self::lpi2c0 as lpi2c4;
pub use self::lpi2c0 as lpi2c5;
pub use self::lpi2c0 as lpi2c6;
pub use self::lpi2c0 as lpi2c7;
pub use self::lpi2c0 as lpi2c8;
pub use self::lpi2c0 as lpi2c9;
pub use self::gpio0 as gpio5;
pub use self::gpio0 as gpio1;
pub use self::gpio0 as gpio2;
pub use self::gpio0 as gpio3;
pub use self::gpio0 as gpio4;
pub use self::edma_0_tcd as edma_1_tcd;
pub use self::cdog0 as cdog1;
pub use self::cmx_perfmon0 as cmx_perfmon1;
pub use self::pwm0 as pwm1;
pub use self::enc0 as enc1;
pub use self::can0 as can1;
pub use self::emvsim0 as emvsim1;
pub use self::sai0 as sai1;
pub use self::adc0 as adc1;
pub use self::dac0 as dac1;
pub use self::opamp0 as opamp1;
pub use self::opamp0 as opamp2;
pub use self::port0 as port1;
pub use self::port0 as port2;
pub use self::port0 as port3;
pub use self::port0 as port4;

Modules§

adc0: ADC
ahbsc: AHBSC
bsp32_0: CoolFlux BSP32
cache64_ctrl0: CACHE64_CTRL
cache64_polsel0: CACHE64_POLSEL
can0: CAN
cdog0: CDOG
cmc0: CMC
cmp0: LPCMP
cmx_perfmon0: CMX_PERFMON
crc0: CRC
ctimer0: CTIMER
dac0: 12-bit DAC
dac2: 14-bit DAC
dm0: DBGMB
dma0: DMA MP
edma_0_tcd: DMA TCD
eim0: EIM
els: no description available
emvsim0: EMVSIM
enc0: ENC
enet0: ENET
erm0: ERM
evtg0: EVTG
ewm0: EWM
flexio0: FLEXIO
flexspi0: FlexSPI
fmu0: Flash
freqme0: FREQME
gdet0: no description available
generic: Common register and bit access and modify traits
gpio0: GPIO
i3c0: I3C
inputmux0: INPUTMUX
intm0: INTM
itrc0: Intrusion and Tamper Response Controller
lp_flexcomm0: LP_FLEXCOMM
lpi2c0: LPI2C
lpspi0: LPSPI
lptmr0: LPTMR
lpuart0: LPUART
mailbox: MAILBOX
mrt0: Multi-Rate Timer (MRT)
npx0: FMC
opamp0: OPAMP
ostimer0: OSTIMER
otpc0: OTPC
pdm: MICFIL
pint0: Pin Interrupts and Pattern Match
pkc0: no description available
plu0: Programmable Logic Unit (PLU)
port0: PORT
powerquad: PowerQuad
puf: PUF
puf_ctrl: PUF Key Context Management
pwm0: PWM
rtc0: RTC
rtc_subsystem0: RTC_SUBSYSTEM
sai0: SAI
sau: no description available
scg0: SCG
scn_scb: no description available
sct0: SCT
sema42_0: SEMA42
sinc0: SINC
sm3_0: SAFO_SM3_SGI
smartdma0: SmartDMA
spc0: SPC
sys_tick0: M33 Systick module
syscon0: SYSCON
tdet0: TDET
trdc: TRDC
trng0: TRNG0
tsi0: TSI
usbdcd0: USBDCD
usbfs0: USBFS
usbhs1__usbc: USB
usbhs1__usbnc: USBNC
usbhs1_phy_dcd: USBDCD
usbphy: USBPHY
usdhc0: uSDHC
utick0: UTICK
vbat0: VBAT
vref0: VREF
wuu0: WUU
wwdt0: WWDT

Structs§

ADC0: ADC
ADC1: ADC
AHBSC: AHBSC
BSP32_0: CoolFlux BSP32
CACHE64_CTRL0: CACHE64_CTRL
CACHE64_POLSEL0: CACHE64_POLSEL
CAN0: CAN
CAN1: CAN
CBP: Cache and branch predictor maintenance operations
CDOG0: CDOG
CDOG1: CDOG
CMC0: CMC
CMP0: LPCMP
CMP1: LPCMP
CMP2: LPCMP
CMX_PERFMON0: CMX_PERFMON
CMX_PERFMON1: CMX_PERFMON
CPUID: CPUID
CRC0: CRC
CTIMER0: CTIMER
CTIMER1: CTIMER
CTIMER2: CTIMER
CTIMER3: CTIMER
CTIMER4: CTIMER
CorePeripherals: Core peripherals
DAC0: 12-bit DAC
DAC1: 12-bit DAC
DAC2: 14-bit DAC
DCB: Debug Control Block
DM0: DBGMB
DMA0: DMA MP
DMA1: DMA MP
DWT: Data Watchpoint and Trace unit
EDMA_0_TCD: DMA TCD
EDMA_1_TCD: DMA TCD
EIM0: EIM
ELS: no description available
EMVSIM0: EMVSIM
EMVSIM1: EMVSIM
ENC0: ENC
ENC1: ENC
ENET0: ENET
ERM0: ERM
EVTG0: EVTG
EWM0: EWM
FLEXIO0: FLEXIO
FLEXSPI0: FlexSPI
FMU0: Flash
FPB: Flash Patch and Breakpoint unit
FPU: Floating Point Unit
FREQME0: FREQME
GDET0: no description available
GDET1: no description available
GPIO0: GPIO
GPIO1: GPIO
GPIO2: GPIO
GPIO3: GPIO
GPIO4: GPIO
GPIO5: GPIO
I3C0: I3C
I3C1: I3C
INPUTMUX0: INPUTMUX
INTM0: INTM
ITM: Instrumentation Trace Macrocell
ITRC0: Intrusion and Tamper Response Controller
LPI2C0: LPI2C
LPI2C1: LPI2C
LPI2C2: LPI2C
LPI2C3: LPI2C
LPI2C4: LPI2C
LPI2C5: LPI2C
LPI2C6: LPI2C
LPI2C7: LPI2C
LPI2C8: LPI2C
LPI2C9: LPI2C
LPSPI0: LPSPI
LPSPI1: LPSPI
LPSPI2: LPSPI
LPSPI3: LPSPI
LPSPI4: LPSPI
LPSPI5: LPSPI
LPSPI6: LPSPI
LPSPI7: LPSPI
LPSPI8: LPSPI
LPSPI9: LPSPI
LPTMR0: LPTMR
LPTMR1: LPTMR
LPUART0: LPUART
LPUART1: LPUART
LPUART2: LPUART
LPUART3: LPUART
LPUART4: LPUART
LPUART5: LPUART
LPUART6: LPUART
LPUART7: LPUART
LPUART8: LPUART
LPUART9: LPUART
LP_FLEXCOMM0: LP_FLEXCOMM
LP_FLEXCOMM1: LP_FLEXCOMM
LP_FLEXCOMM2: LP_FLEXCOMM
LP_FLEXCOMM3: LP_FLEXCOMM
LP_FLEXCOMM4: LP_FLEXCOMM
LP_FLEXCOMM5: LP_FLEXCOMM
LP_FLEXCOMM6: LP_FLEXCOMM
LP_FLEXCOMM7: LP_FLEXCOMM
LP_FLEXCOMM8: LP_FLEXCOMM
LP_FLEXCOMM9: LP_FLEXCOMM
MAILBOX: MAILBOX
MPU: Memory Protection Unit
MRT0: Multi-Rate Timer (MRT)
NPX0: FMC
NVIC: Nested Vector Interrupt Controller
OPAMP0: OPAMP
OPAMP1: OPAMP
OPAMP2: OPAMP
OSTIMER0: OSTIMER
OTPC0: OTPC
PDM: MICFIL
PINT0: Pin Interrupts and Pattern Match
PKC0: no description available
PLU0: Programmable Logic Unit (PLU)
PORT0: PORT
PORT1: PORT
PORT2: PORT
PORT3: PORT
PORT4: PORT
PORT5: PORT
POWERQUAD: PowerQuad
PUF: PUF
PUF_CTRL: PUF Key Context Management
PWM0: PWM
PWM1: PWM
Peripherals: All the peripherals.
RTC0: RTC
RTC_SUBSYSTEM0: RTC_SUBSYSTEM
SAI0: SAI
SAI1: SAI
SAU: no description available
SCB: System Control Block
SCG0: SCG
SCN_SCB: no description available
SCT0: SCT
SEMA42_0: SEMA42
SINC0: SINC
SM3_0: SAFO_SM3_SGI
SMARTDMA0: SmartDMA
SPC0: SPC
SYSCON0: SYSCON
SYST: SysTick: System Timer
SYS_TICK0: M33 Systick module
TDET0: TDET
TPIU: Trace Port Interface Unit
TRDC: TRDC
TRNG0: TRNG0
TSI0: TSI
USBDCD0: USBDCD
USBFS0: USBFS
USBHS1_PHY_DCD: USBDCD
USBHS1__USBC: USB
USBHS1__USBNC: USBNC
USBPHY: USBPHY
USDHC0: uSDHC
UTICK0: UTICK
VBAT0: VBAT
VREF0: VREF
WUU0: WUU
WWDT0: WWDT
WWDT1: WWDT

Enums§

Interrupt: Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS: Number available in the NVIC for configuring priority

Attribute Macros§

interrupt