Module mcxn947_pac::i3c0

I3C

Modules

• ibiext1
  Extended IBI Data 1
• ibiext2
  Extended IBI Data 2
• mconfig
  Controller Configuration
• mctrl
  Controller Control
• mdatactrl
  Controller Data Control
• mdmactrl
  Controller DMA Control
• mdynaddr
  Controller Dynamic Address
• merrwarn
  Controller Errors and Warnings
• mibirules
  Controller In-band Interrupt Registry and Rules
• mintclr
  Controller Interrupt Clear
• mintmasked
  Controller Interrupt Mask
• mintset
  Controller Interrupt Set
• mrdatab
  Controller Read Data Byte
• mrdatah
  Controller Read Data Halfword
• mrmsg_ddr
  Controller Read Message in DDR mode
• mrmsg_sdr
  Controller Read Message in SDR mode
• mstatus
  Controller Status
• mwdatab
  Controller Write Data Byte
• mwdatab1
  Controller Write Byte Data 1(to bus)
• mwdatabe
  Controller Write Data Byte End
• mwdatah
  Controller Write Data Halfword
• mwdatahe
  Controller Write Data Halfword End
• mwmsg_ddr_mwmsg_ddr_control
  Controller Write Message in DDR mode: First Control Word
• mwmsg_ddr_mwmsg_ddr_control2
  Controller Write Message in DDR mode Control 2
• mwmsg_ddr_mwmsg_ddr_data
  Controller Write Message Data in DDR mode
• mwmsg_sdr_mwmsg_sdr_control
  Controller Write Message Control in SDR mode
• mwmsg_sdr_mwmsg_sdr_data
  Controller Write Message Data in SDR mode
• scapabilities
  Target Capabilities
• scapabilities2
  Target Capabilities 2
• sconfig
  Target Configuration
• sctrl
  Target Control
• sdatactrl
  Target Data Control
• sdmactrl
  Target DMA Control
• sdynaddr
  Target Dynamic Address
• serrwarn
  Target Errors and Warnings
• sid
  Target Module ID
• sidext
  Target ID Extension
• sidpartno
  Target ID Part Number
• sintclr
  Target Interrupt Clear
• sintmasked
  Target Interrupt Mask
• sintset
  Target Interrupt Set
• smapctrl0
  Map Feature Control 0
• smaxlimits
  Target Maximum Limits
• smsgmapaddr
  Target Message Map Address
• srdatab
  Target Read Data Byte
• srdatah
  Target Read Data Halfword
• sstatus
  Target Status
• stcclock
  Target Time Control Clock
• svendorid
  Target Vendor ID
• swdatab
  Target Write Data Byte
• swdatab1
  Target Write Data Byte
• swdatabe
  Target Write Data Byte End
• swdatah
  Target Write Data Half-word
• swdatahe
  Target Write Data Half-word End

Structs

• RegisterBlock
  Register block

Type Aliases

• IBIEXT1
  IBIEXT1 (rw) register accessor: Extended IBI Data 1
• IBIEXT2
  IBIEXT2 (rw) register accessor: Extended IBI Data 2
• MCONFIG
  MCONFIG (rw) register accessor: Controller Configuration
• MCTRL
  MCTRL (rw) register accessor: Controller Control
• MDATACTRL
  MDATACTRL (rw) register accessor: Controller Data Control
• MDMACTRL
  MDMACTRL (rw) register accessor: Controller DMA Control
• MDYNADDR
  MDYNADDR (rw) register accessor: Controller Dynamic Address
• MERRWARN
  MERRWARN (rw) register accessor: Controller Errors and Warnings
• MIBIRULES
  MIBIRULES (rw) register accessor: Controller In-band Interrupt Registry and Rules
• MINTCLR
  MINTCLR (rw) register accessor: Controller Interrupt Clear
• MINTMASKED
  MINTMASKED (r) register accessor: Controller Interrupt Mask
• MINTSET
  MINTSET (rw) register accessor: Controller Interrupt Set
• MRDATAB
  MRDATAB (r) register accessor: Controller Read Data Byte
• MRDATAH
  MRDATAH (r) register accessor: Controller Read Data Halfword
• MRMSG_DDR
  MRMSG_DDR (r) register accessor: Controller Read Message in DDR mode
• MRMSG_SDR
  MRMSG_SDR (r) register accessor: Controller Read Message in SDR mode
• MSTATUS
  MSTATUS (rw) register accessor: Controller Status
• MWDATAB
  MWDATAB (w) register accessor: Controller Write Data Byte
• MWDATAB1
  MWDATAB1 (w) register accessor: Controller Write Byte Data 1(to bus)
• MWDATABE
  MWDATABE (w) register accessor: Controller Write Data Byte End
• MWDATAH
  MWDATAH (w) register accessor: Controller Write Data Halfword
• MWDATAHE
  MWDATAHE (w) register accessor: Controller Write Data Halfword End
• MWMSG_DDR_MWMSG_DDR_CONTROL
  MWMSG_DDR_MWMSG_DDR_CONTROL (w) register accessor: Controller Write Message in DDR mode: First Control Word
• MWMSG_DDR_MWMSG_DDR_CONTROL2
  MWMSG_DDR_MWMSG_DDR_CONTROL2 (w) register accessor: Controller Write Message in DDR mode Control 2
• MWMSG_DDR_MWMSG_DDR_DATA
  MWMSG_DDR_MWMSG_DDR_DATA (w) register accessor: Controller Write Message Data in DDR mode
• MWMSG_SDR_MWMSG_SDR_CONTROL
  MWMSG_SDR_MWMSG_SDR_CONTROL (w) register accessor: Controller Write Message Control in SDR mode
• MWMSG_SDR_MWMSG_SDR_DATA
  MWMSG_SDR_MWMSG_SDR_DATA (w) register accessor: Controller Write Message Data in SDR mode
• SCAPABILITIES
  SCAPABILITIES (r) register accessor: Target Capabilities
• SCAPABILITIES2
  SCAPABILITIES2 (r) register accessor: Target Capabilities 2
• SCONFIG
  SCONFIG (rw) register accessor: Target Configuration
• SCTRL
  SCTRL (rw) register accessor: Target Control
• SDATACTRL
  SDATACTRL (rw) register accessor: Target Data Control
• SDMACTRL
  SDMACTRL (rw) register accessor: Target DMA Control
• SDYNADDR
  SDYNADDR (rw) register accessor: Target Dynamic Address
• SERRWARN
  SERRWARN (rw) register accessor: Target Errors and Warnings
• SID
  SID (r) register accessor: Target Module ID
• SIDEXT
  SIDEXT (rw) register accessor: Target ID Extension
• SIDPARTNO
  SIDPARTNO (rw) register accessor: Target ID Part Number
• SINTCLR
  SINTCLR (rw) register accessor: Target Interrupt Clear
• SINTMASKED
  SINTMASKED (r) register accessor: Target Interrupt Mask
• SINTSET
  SINTSET (rw) register accessor: Target Interrupt Set
• SMAPCTRL0
  SMAPCTRL0 (r) register accessor: Map Feature Control 0
• SMAXLIMITS
  SMAXLIMITS (rw) register accessor: Target Maximum Limits
• SMSGMAPADDR
  SMSGMAPADDR (r) register accessor: Target Message Map Address
• SRDATAB
  SRDATAB (r) register accessor: Target Read Data Byte
• SRDATAH
  SRDATAH (r) register accessor: Target Read Data Halfword
• SSTATUS
  SSTATUS (rw) register accessor: Target Status
• STCCLOCK
  STCCLOCK (rw) register accessor: Target Time Control Clock
• SVENDORID
  SVENDORID (rw) register accessor: Target Vendor ID
• SWDATAB
  SWDATAB (w) register accessor: Target Write Data Byte
• SWDATAB1
  SWDATAB1 (w) register accessor: Target Write Data Byte
• SWDATABE
  SWDATABE (w) register accessor: Target Write Data Byte End
• SWDATAH
  SWDATAH (w) register accessor: Target Write Data Half-word
• SWDATAHE
  SWDATAHE (w) register accessor: Target Write Data Half-word End