Module mcxn947_pac::flexspi0

FlexSPI

Re-exports

• pub use self::ipedctx::IPEDCTX;

Modules

• ahbbufregionend
  Receive Buffer Region %s End Address
• ahbbufregionstart
  Receive Buffer Start Address of Region %s
• ahbcr
  AHB Bus Control
• ahbrxbufcr0
  AHB Receive Buffer %s Control 0
• ahbspndsts
  AHB Suspend Status
• dllcr
  DLL Control 0
• dlpr
  Data Learning Pattern
• flashcr0
  Flash Control 0
• flshcr1
  Flash Control 1
• flshcr2
  Flash Control 2
• flshcr4
  Flash Control 4
• haddrend
  HADDR REMAP END ADDR
• haddroffset
  HADDR Remap Offset
• haddrstart
  HADDR REMAP Start Address
• inten
  Interrupt Enable
• intr
  Interrupt
• ipcmd
  IP Command
• ipcr0
  IP Control 0
• ipcr1
  IP Control 1
• ipcr2
  IP Control 2
• ipedctrl
  IPED Function Control
• ipedctx
  Cluster Cluster IPEDCTX%s, containing IPEDCTX?IV0, IPEDCTX?IV1, IPEDCTX?START, IPEDCTX?END, IPEDCTX?AAD0, IPEDCTX?AAD1
• ipedctxctrl0
  IPED context control 0
• ipedctxctrl1
  IPED context control 1
• iprxfcr
  IP Receive FIFO Control
• iprxfsts
  IP Receive FIFO Status
• ipsnszend0
  IPS Nonsecure Region 0 End Address
• ipsnszend1
  IPS Nonsecure Region 1 End Address
• ipsnszstart0
  IPS Nonsecure Region 0 Start Address
• ipsnszstart1
  IPS Nonsecure Region 1 Start Address
• iptxfcr
  IP Transmit FIFO Control
• iptxfsts
  IP Transmit FIFO Status
• lut
  Lookup Table x
• lutcr
  LUT Control
• lutkey
  LUT Key
• mcr0
  Module Control 0
• mcr1
  Module Control 1
• mcr2
  Module Control 2
• rfdr
  IP Receive FIFO Data x
• sts0
  Status 0
• sts1
  Status 1
• sts2
  Status 2
• tfdr
  IP TX FIFO Data x

Structs

• RegisterBlock
  Register block

Type Aliases

• AHBBUFREGIONEND
  AHBBUFREGIONEND (rw) register accessor: Receive Buffer Region %s End Address
• AHBBUFREGIONSTART
  AHBBUFREGIONSTART (rw) register accessor: Receive Buffer Start Address of Region %s
• AHBCR
  AHBCR (rw) register accessor: AHB Bus Control
• AHBRXBUFCR0
  AHBRXBUFCR0 (rw) register accessor: AHB Receive Buffer %s Control 0
• AHBSPNDSTS
  AHBSPNDSTS (r) register accessor: AHB Suspend Status
• DLLCR
  DLLCR (rw) register accessor: DLL Control 0
• DLPR
  DLPR (rw) register accessor: Data Learning Pattern
• FLASHCR0
  FLASHCR0 (rw) register accessor: Flash Control 0
• FLSHCR1
  FLSHCR1 (rw) register accessor: Flash Control 1
• FLSHCR2
  FLSHCR2 (rw) register accessor: Flash Control 2
• FLSHCR4
  FLSHCR4 (rw) register accessor: Flash Control 4
• HADDREND
  HADDREND (rw) register accessor: HADDR REMAP END ADDR
• HADDROFFSET
  HADDROFFSET (rw) register accessor: HADDR Remap Offset
• HADDRSTART
  HADDRSTART (rw) register accessor: HADDR REMAP Start Address
• INTEN
  INTEN (rw) register accessor: Interrupt Enable
• INTR
  INTR (rw) register accessor: Interrupt
• IPCMD
  IPCMD (rw) register accessor: IP Command
• IPCR0
  IPCR0 (rw) register accessor: IP Control 0
• IPCR1
  IPCR1 (rw) register accessor: IP Control 1
• IPCR2
  IPCR2 (rw) register accessor: IP Control 2
• IPEDCTRL
  IPEDCTRL (rw) register accessor: IPED Function Control
• IPEDCTXCTRL0
  IPEDCTXCTRL0 (rw) register accessor: IPED context control 0
• IPEDCTXCTRL1
  IPEDCTXCTRL1 (rw) register accessor: IPED context control 1
• IPRXFCR
  IPRXFCR (rw) register accessor: IP Receive FIFO Control
• IPRXFSTS
  IPRXFSTS (r) register accessor: IP Receive FIFO Status
• IPSNSZEND0
  IPSNSZEND0 (rw) register accessor: IPS Nonsecure Region 0 End Address
• IPSNSZEND1
  IPSNSZEND1 (rw) register accessor: IPS Nonsecure Region 1 End Address
• IPSNSZSTART0
  IPSNSZSTART0 (rw) register accessor: IPS Nonsecure Region 0 Start Address
• IPSNSZSTART1
  IPSNSZSTART1 (rw) register accessor: IPS Nonsecure Region 1 Start Address
• IPTXFCR
  IPTXFCR (rw) register accessor: IP Transmit FIFO Control
• IPTXFSTS
  IPTXFSTS (r) register accessor: IP Transmit FIFO Status
• LUT
  LUT (rw) register accessor: Lookup Table x
• LUTCR
  LUTCR (rw) register accessor: LUT Control
• LUTKEY
  LUTKEY (rw) register accessor: LUT Key
• MCR0
  MCR0 (rw) register accessor: Module Control 0
• MCR1
  MCR1 (rw) register accessor: Module Control 1
• MCR2
  MCR2 (rw) register accessor: Module Control 2
• RFDR
  RFDR (r) register accessor: IP Receive FIFO Data x
• STS0
  STS0 (r) register accessor: Status 0
• STS1
  STS1 (r) register accessor: Status 1
• STS2
  STS2 (r) register accessor: Status 2
• TFDR
  TFDR (w) register accessor: IP TX FIFO Data x