Module mcxn947_pac::tsi0

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TSI

Modules§

Structs§

Type Aliases§

  • BASELINE
    BASELINE (rw) register accessor: TSI Baseline
  • CHMERGE
    CHMERGE (rw) register accessor: TSI Channel Merge
  • CONFIG_CONFIG
    CONFIG_CONFIG (rw) register accessor: TSI CONFIG (TSI_CONFIG) for Self-Capacitor
  • CONFIG_CONFIG_MUTUAL
    CONFIG_CONFIG_MUTUAL (rw) register accessor: TSI CONFIG (TSI_CONFIG) for Mutual-Capacitor
  • DATA
    DATA (rw) register accessor: TSI Data and Status
  • GENCS
    GENCS (rw) register accessor: TSI General Control and Status
  • MISC
    MISC (rw) register accessor: TSI Miscellaneous
  • MUL
    MUL (rw) register accessor: TSI Mutual-Capacitance
  • SHIELD
    SHIELD (rw) register accessor: TSI Shield
  • SINC
    SINC (rw) register accessor: TSI SINC Filter
  • SSC0
    SSC0 (rw) register accessor: TSI SSC 0
  • SSC1
    SSC1 (rw) register accessor: TSI SSC 1
  • SSC2
    SSC2 (rw) register accessor: TSI SSC 2
  • TRIG
    TRIG (rw) register accessor: TSI AUTO TRIG
  • TSHD
    TSHD (rw) register accessor: TSI Threshold