Module mcxn947_pac::lpi2c0

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LPI2C

Modules§

  • mccr0
    Controller Clock Configuration 0
  • mccr1
    Controller Clock Configuration 1
  • mcfgr0
    Controller Configuration 0
  • mcfgr1
    Controller Configuration 1
  • mcfgr2
    Controller Configuration 2
  • mcfgr3
    Controller Configuration 3
  • mcr
    Controller Control
  • mder
    Controller DMA Enable
  • mdmr
    Controller Data Match
  • mfcr
    Controller FIFO Control
  • mfsr
    Controller FIFO Status
  • mier
    Controller Interrupt Enable
  • mrdr
    Controller Receive Data
  • mrdror
    Controller Receive Data Read Only
  • msr
    Controller Status
  • mtcbr
    Controller Transmit Command Burst
  • mtdbr
    Transmit Data Burst
  • mtdr
    Controller Transmit Data
  • param
    Parameter
  • samr
    Target Address Match
  • sasr
    Target Address Status
  • scfgr0
    Target Configuration 0
  • scfgr1
    Target Configuration 1
  • scfgr2
    Target Configuration 2
  • scr
    Target Control
  • sder
    Target DMA Enable
  • sier
    Target interrupt enable
  • srdr
    Target Receive Data
  • srdror
    Target Receive Data Read Only
  • ssr
    Target Status
  • star
    Target Transmit ACK
  • stdr
    Target Transmit Data
  • verid
    Version ID

Structs§

Type Aliases§

  • MCCR0
    MCCR0 (rw) register accessor: Controller Clock Configuration 0
  • MCCR1
    MCCR1 (rw) register accessor: Controller Clock Configuration 1
  • MCFGR0
    MCFGR0 (rw) register accessor: Controller Configuration 0
  • MCFGR1
    MCFGR1 (rw) register accessor: Controller Configuration 1
  • MCFGR2
    MCFGR2 (rw) register accessor: Controller Configuration 2
  • MCFGR3
    MCFGR3 (rw) register accessor: Controller Configuration 3
  • MCR
    MCR (rw) register accessor: Controller Control
  • MDER
    MDER (rw) register accessor: Controller DMA Enable
  • MDMR
    MDMR (rw) register accessor: Controller Data Match
  • MFCR
    MFCR (rw) register accessor: Controller FIFO Control
  • MFSR
    MFSR (r) register accessor: Controller FIFO Status
  • MIER
    MIER (rw) register accessor: Controller Interrupt Enable
  • MRDR
    MRDR (r) register accessor: Controller Receive Data
  • MRDROR
    MRDROR (r) register accessor: Controller Receive Data Read Only
  • MSR
    MSR (rw) register accessor: Controller Status
  • MTCBR
    MTCBR (w) register accessor: Controller Transmit Command Burst
  • MTDBR
    MTDBR (w) register accessor: Transmit Data Burst
  • MTDR
    MTDR (w) register accessor: Controller Transmit Data
  • PARAM
    PARAM (r) register accessor: Parameter
  • SAMR
    SAMR (rw) register accessor: Target Address Match
  • SASR
    SASR (r) register accessor: Target Address Status
  • SCFGR0
    SCFGR0 (rw) register accessor: Target Configuration 0
  • SCFGR1
    SCFGR1 (rw) register accessor: Target Configuration 1
  • SCFGR2
    SCFGR2 (rw) register accessor: Target Configuration 2
  • SCR
    SCR (rw) register accessor: Target Control
  • SDER
    SDER (rw) register accessor: Target DMA Enable
  • SIER
    SIER (rw) register accessor: Target interrupt enable
  • SRDR
    SRDR (r) register accessor: Target Receive Data
  • SRDROR
    SRDROR (r) register accessor: Target Receive Data Read Only
  • SSR
    SSR (rw) register accessor: Target Status
  • STAR
    STAR (rw) register accessor: Target Transmit ACK
  • STDR
    STDR (w) register accessor: Target Transmit Data
  • VERID
    VERID (r) register accessor: Version ID