Module mcxn947_pac::i3c0
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I3C
Modules§
- Extended IBI Data 1
- Extended IBI Data 2
- Controller Configuration
- Controller Control
- Controller Data Control
- Controller DMA Control
- Controller Dynamic Address
- Controller Errors and Warnings
- Controller In-band Interrupt Registry and Rules
- Controller Interrupt Clear
- Controller Interrupt Mask
- Controller Interrupt Set
- Controller Read Data Byte
- Controller Read Data Halfword
- Controller Read Message in DDR mode
- Controller Read Message in SDR mode
- Controller Status
- Controller Write Data Byte
- Controller Write Byte Data 1(to bus)
- Controller Write Data Byte End
- Controller Write Data Halfword
- Controller Write Data Halfword End
- Controller Write Message in DDR mode: First Control Word
- Controller Write Message in DDR mode Control 2
- Controller Write Message Data in DDR mode
- Controller Write Message Control in SDR mode
- Controller Write Message Data in SDR mode
- Target Capabilities
- Target Capabilities 2
- Target Configuration
- Target Control
- Target Data Control
- Target DMA Control
- Target Dynamic Address
- Target Errors and Warnings
- Target Module ID
- Target ID Extension
- Target ID Part Number
- Target Interrupt Clear
- Target Interrupt Mask
- Target Interrupt Set
- Map Feature Control 0
- Target Maximum Limits
- Target Message Map Address
- Target Read Data Byte
- Target Read Data Halfword
- Target Status
- Target Time Control Clock
- Target Vendor ID
- Target Write Data Byte
- Target Write Data Byte
- Target Write Data Byte End
- Target Write Data Half-word
- Target Write Data Half-word End
Structs§
- Register block
Type Aliases§
- IBIEXT1 (rw) register accessor: Extended IBI Data 1
- IBIEXT2 (rw) register accessor: Extended IBI Data 2
- MCONFIG (rw) register accessor: Controller Configuration
- MCTRL (rw) register accessor: Controller Control
- MDATACTRL (rw) register accessor: Controller Data Control
- MDMACTRL (rw) register accessor: Controller DMA Control
- MDYNADDR (rw) register accessor: Controller Dynamic Address
- MERRWARN (rw) register accessor: Controller Errors and Warnings
- MIBIRULES (rw) register accessor: Controller In-band Interrupt Registry and Rules
- MINTCLR (rw) register accessor: Controller Interrupt Clear
- MINTMASKED (r) register accessor: Controller Interrupt Mask
- MINTSET (rw) register accessor: Controller Interrupt Set
- MRDATAB (r) register accessor: Controller Read Data Byte
- MRDATAH (r) register accessor: Controller Read Data Halfword
- MRMSG_DDR (r) register accessor: Controller Read Message in DDR mode
- MRMSG_SDR (r) register accessor: Controller Read Message in SDR mode
- MSTATUS (rw) register accessor: Controller Status
- MWDATAB (w) register accessor: Controller Write Data Byte
- MWDATAB1 (w) register accessor: Controller Write Byte Data 1(to bus)
- MWDATABE (w) register accessor: Controller Write Data Byte End
- MWDATAH (w) register accessor: Controller Write Data Halfword
- MWDATAHE (w) register accessor: Controller Write Data Halfword End
- MWMSG_DDR_MWMSG_DDR_CONTROL (w) register accessor: Controller Write Message in DDR mode: First Control Word
- MWMSG_DDR_MWMSG_DDR_CONTROL2 (w) register accessor: Controller Write Message in DDR mode Control 2
- MWMSG_DDR_MWMSG_DDR_DATA (w) register accessor: Controller Write Message Data in DDR mode
- MWMSG_SDR_MWMSG_SDR_CONTROL (w) register accessor: Controller Write Message Control in SDR mode
- MWMSG_SDR_MWMSG_SDR_DATA (w) register accessor: Controller Write Message Data in SDR mode
- SCAPABILITIES (r) register accessor: Target Capabilities
- SCAPABILITIES2 (r) register accessor: Target Capabilities 2
- SCONFIG (rw) register accessor: Target Configuration
- SCTRL (rw) register accessor: Target Control
- SDATACTRL (rw) register accessor: Target Data Control
- SDMACTRL (rw) register accessor: Target DMA Control
- SDYNADDR (rw) register accessor: Target Dynamic Address
- SERRWARN (rw) register accessor: Target Errors and Warnings
- SID (r) register accessor: Target Module ID
- SIDEXT (rw) register accessor: Target ID Extension
- SIDPARTNO (rw) register accessor: Target ID Part Number
- SINTCLR (rw) register accessor: Target Interrupt Clear
- SINTMASKED (r) register accessor: Target Interrupt Mask
- SINTSET (rw) register accessor: Target Interrupt Set
- SMAPCTRL0 (r) register accessor: Map Feature Control 0
- SMAXLIMITS (rw) register accessor: Target Maximum Limits
- SMSGMAPADDR (r) register accessor: Target Message Map Address
- SRDATAB (r) register accessor: Target Read Data Byte
- SRDATAH (r) register accessor: Target Read Data Halfword
- SSTATUS (rw) register accessor: Target Status
- STCCLOCK (rw) register accessor: Target Time Control Clock
- SVENDORID (rw) register accessor: Target Vendor ID
- SWDATAB (w) register accessor: Target Write Data Byte
- SWDATAB1 (w) register accessor: Target Write Data Byte
- SWDATABE (w) register accessor: Target Write Data Byte End
- SWDATAH (w) register accessor: Target Write Data Half-word
- SWDATAHE (w) register accessor: Target Write Data Half-word End