Module mcxn947_pac::sm3_0

SAFO_SM3_SGI

Modules

• config
  SGI Configuration Register
• count
  Calculation Counter
• ctrl
  SGI Control Register
• ctrl2
  SGI Control Register 2
• datin0a
  Input Data register 0 lower-bank low
• datin0b
  Input Data register 0 lower-bank high
• datin0c
  Input Data register 0 upper-bank low
• datin0d
  Input Data register 0 upper-bank high
• datin1a
  Input Data register 1 lower-bank low
• datin1b
  Input Data register 1 lower-bank high
• datin1c
  Input Data register 1 upper-bank low
• datin1d
  Input Data register 1 upper-bank high
• datouta
  Output Data register lower-bank low
• datoutb
  Ouput Data register lower-bank high
• datoutc
  Ouput Data register upper-bank low
• datoutd
  Output Data register upper-bank high
• int_enable
  Interrupt Enable
• int_status_clr
  Interrupt Status Clear
• int_status_set
  Interrupt Status Set
• key0a
  Input Key register 0 lower-bank low
• key0b
  Input Key register 0 lower-bank high
• key0c
  Input Key register 0 upper-bank low
• key0d
  Input Key register 0 upper-bank high
• key1a
  Input Key register 1 lower-bank low
• key1b
  Input Key register 1 lower-bank high
• key1c
  Input Key register 1 upper-bank low
• key1d
  Input Key register 1 upper-bank high
• sm3_ctrl
  SM3 Control Register
• sm3_fifo
  SM3 FIFO Register
• status
  Status Register

Structs

• RegisterBlock
  Register block

Type Aliases

• CONFIG
  CONFIG (r) register accessor: SGI Configuration Register
• COUNT
  COUNT (rw) register accessor: Calculation Counter
• CTRL
  CTRL (rw) register accessor: SGI Control Register
• CTRL2
  CTRL2 (rw) register accessor: SGI Control Register 2
• DATIN0A
  DATIN0A (rw) register accessor: Input Data register 0 lower-bank low
• DATIN0B
  DATIN0B (rw) register accessor: Input Data register 0 lower-bank high
• DATIN0C
  DATIN0C (rw) register accessor: Input Data register 0 upper-bank low
• DATIN0D
  DATIN0D (rw) register accessor: Input Data register 0 upper-bank high
• DATIN1A
  DATIN1A (rw) register accessor: Input Data register 1 lower-bank low
• DATIN1B
  DATIN1B (rw) register accessor: Input Data register 1 lower-bank high
• DATIN1C
  DATIN1C (rw) register accessor: Input Data register 1 upper-bank low
• DATIN1D
  DATIN1D (rw) register accessor: Input Data register 1 upper-bank high
• DATOUTA
  DATOUTA (r) register accessor: Output Data register lower-bank low
• DATOUTB
  DATOUTB (r) register accessor: Ouput Data register lower-bank high
• DATOUTC
  DATOUTC (r) register accessor: Ouput Data register upper-bank low
• DATOUTD
  DATOUTD (r) register accessor: Output Data register upper-bank high
• INT_ENABLE
  INT_ENABLE (rw) register accessor: Interrupt Enable
• INT_STATUS_CLR
  INT_STATUS_CLR (w) register accessor: Interrupt Status Clear
• INT_STATUS_SET
  INT_STATUS_SET (w) register accessor: Interrupt Status Set
• KEY0A
  KEY0A (rw) register accessor: Input Key register 0 lower-bank low
• KEY0B
  KEY0B (rw) register accessor: Input Key register 0 lower-bank high
• KEY0C
  KEY0C (rw) register accessor: Input Key register 0 upper-bank low
• KEY0D
  KEY0D (rw) register accessor: Input Key register 0 upper-bank high
• KEY1A
  KEY1A (rw) register accessor: Input Key register 1 lower-bank low
• KEY1B
  KEY1B (rw) register accessor: Input Key register 1 lower-bank high
• KEY1C
  KEY1C (rw) register accessor: Input Key register 1 upper-bank low
• KEY1D
  KEY1D (rw) register accessor: Input Key register 1 upper-bank high
• SM3_CTRL
  SM3_CTRL (rw) register accessor: SM3 Control Register
• SM3_FIFO
  SM3_FIFO (rw) register accessor: SM3 FIFO Register
• STATUS
  STATUS (r) register accessor: Status Register