Module mcxn947_pac::ahbsc

AHBSC

Re-exports

• pub use self::flexspi0_region1_6_mem_rule::FLEXSPI0_REGION1_6_MEM_RULE;
• pub use self::flexspi0_region8_13_mem_rule::FLEXSPI0_REGION8_13_MEM_RULE;

Modules

• ahb_peripheral0_slave_port_p12_slave_rule0
  AHB Peripheral 0 Slave Port 12 Slave Rule 0
• ahb_peripheral0_slave_port_p12_slave_rule1
  AHB Peripheral 0 Slave Port 12 Slave Rule 1
• ahb_peripheral0_slave_port_p12_slave_rule2
  AHB Peripheral 0 Slave Port 12 Slave Rule 2
• ahb_peripheral1_slave_port_p13_slave_rule0
  AHB Peripheral 1 Slave Port 13 Slave Rule 0
• ahb_peripheral1_slave_port_p13_slave_rule1
  AHB Peripheral 1 Slave Port 13 Slave Rule 1
• ahb_peripheral1_slave_port_p13_slave_rule2
  AHB Peripheral 1 Slave Port 13 Slave Rule 2
• ahb_secure_ctrl_peripheral_rule0
  AHB Secure Control Peripheral Rule 0
• aips_bridge_group0_mem_rule0
  AIPS Bridge Group 0 Memory Rule 0
• aips_bridge_group0_mem_rule1
  AIPS Bridge Group 0 Memory Rule 1
• aips_bridge_group0_mem_rule2
  AIPS Bridge Group 0 Memory Rule 2
• aips_bridge_group0_mem_rule3
  AIPS Bridge Group 0 Memory Rule 3
• aips_bridge_group1_mem_rule0
  AIPS Bridge Group 1 Rule 0
• aips_bridge_group1_mem_rule1
  AIPS Bridge Group 1 Rule 1
• aips_bridge_group2_mem_rule0
  AIPS Bridge Group 2 Rule 0
• aips_bridge_group2_mem_rule1
  AIPS Bridge Group 2 Memory Rule 1
• aips_bridge_group3_mem_rule0
  AIPS Bridge Group 3 Rule 0
• aips_bridge_group3_mem_rule1
  AIPS Bridge Group 3 Memory Rule 1
• aips_bridge_group3_mem_rule2
  AIPS Bridge Group 3 Rule 2
• aips_bridge_group3_mem_rule3
  AIPS Bridge Group 3 Rule 3
• aips_bridge_group4_mem_rule0
  AIPS Bridge Group 4 Rule 0
• aips_bridge_group4_mem_rule1
  AIPS Bridge Group 4 Rule 1
• aips_bridge_group4_mem_rule2
  AIPS Bridge Group 4 Rule 2
• aips_bridge_group4_mem_rule3
  AIPS Bridge Group 4 Rule 3
• apb_peripheral_group0_mem_rule0
  APB Bridge Group 0 Memory Rule 0
• apb_peripheral_group0_mem_rule1
  APB Bridge Group 0 Memory Rule 1
• apb_peripheral_group0_mem_rule2
  APB Bridge Group 0 Rule 2
• apb_peripheral_group0_mem_rule3
  APB Bridge Group 0 Memory Rule 3
• apb_peripheral_group1_mem_rule0
  APB Bridge Group 1 Memory Rule 0
• apb_peripheral_group1_mem_rule1
  APB Bridge Group 1 Memory Rule 1
• apb_peripheral_group1_mem_rule2
  APB Bridge Group 1 Memory Rule 2
• cpu0_lock_reg
  Miscellaneous CPU0 Control Signals
• cpu1_lock_reg
  Miscellaneous CPU1 Control Signals
• flash00_mem_rule
  Flash Memory Rule
• flash01_mem_rule
  Flash Memory Rule
• flash02_mem_rule
  Flash Memory Rule
• flash03_mem_rule
  Flash Memory Rule
• flexspi0_region0_mem_rule
  FLEXSPI0 Region 0 Memory Rule
• flexspi0_region1_6_mem_rule
  Cluster no description available
• flexspi0_region7_mem_rule
  FLEXSPI0 Region 7 Memory Rule
• flexspi0_region8_13_mem_rule
  Cluster no description available
• master_sec_anti_pol_reg
  Master Secure Level
• master_sec_level
  Master Secure Level
• misc_ctrl_dp_reg
  Secure Control Duplicate
• misc_ctrl_reg
  Secure Control
• rama_mem_rule
  RAMA Memory Rule 0
• ramb_mem_rule
  RAMB Memory Rule
• ramc_mem_rule
  RAMC Memory Rule
• ramd_mem_rule
  RAMD Memory Rule
• rame_mem_rule
  RAME Memory Rule
• ramf_mem_rule
  RAMF Memory Rule
• ramg_mem_rule
  RAMG Memory Rule
• ramh_mem_rule
  RAMH Memory Rule
• ramx_mem_rule
  RAMX Memory Rule
• rom_mem_rule
  ROM Memory Rule
• sec_cpu1_int_mask0
  Secure Interrupt Mask 0 for CPU1
• sec_cpu1_int_mask1
  Secure Interrupt Mask 1 for CPU1
• sec_cpu1_int_mask2
  Secure Interrupt Mask 2 for CPU1
• sec_cpu1_int_mask3
  Secure Interrupt Mask 3 for CPU1
• sec_cpu1_int_mask4
  Secure Interrupt Mask 4 for CPU1
• sec_gp_reg_lock
  Secure Mask Lock
• sec_gpio_mask
  GPIO Mask for Port index
• sec_vio_addr
  Security Violation Address
• sec_vio_info_valid
  Security Violation Info Validity for Address
• sec_vio_misc_info
  Security Violation Miscellaneous Information at Address

Structs

• RegisterBlock
  Register block

Type Aliases

• AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0
  AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0 (rw) register accessor: AHB Peripheral 0 Slave Port 12 Slave Rule 0
• AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1
  AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1 (rw) register accessor: AHB Peripheral 0 Slave Port 12 Slave Rule 1
• AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2
  AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2 (rw) register accessor: AHB Peripheral 0 Slave Port 12 Slave Rule 2
• AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0
  AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0 (rw) register accessor: AHB Peripheral 1 Slave Port 13 Slave Rule 0
• AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1
  AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1 (rw) register accessor: AHB Peripheral 1 Slave Port 13 Slave Rule 1
• AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2
  AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2 (rw) register accessor: AHB Peripheral 1 Slave Port 13 Slave Rule 2
• AHB_SECURE_CTRL_PERIPHERAL_RULE0
  AHB_SECURE_CTRL_PERIPHERAL_RULE0 (rw) register accessor: AHB Secure Control Peripheral Rule 0
• AIPS_BRIDGE_GROUP0_MEM_RULE0
  AIPS_BRIDGE_GROUP0_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 0 Memory Rule 0
• AIPS_BRIDGE_GROUP0_MEM_RULE1
  AIPS_BRIDGE_GROUP0_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 0 Memory Rule 1
• AIPS_BRIDGE_GROUP0_MEM_RULE2
  AIPS_BRIDGE_GROUP0_MEM_RULE2 (rw) register accessor: AIPS Bridge Group 0 Memory Rule 2
• AIPS_BRIDGE_GROUP0_MEM_RULE3
  AIPS_BRIDGE_GROUP0_MEM_RULE3 (rw) register accessor: AIPS Bridge Group 0 Memory Rule 3
• AIPS_BRIDGE_GROUP1_MEM_RULE0
  AIPS_BRIDGE_GROUP1_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 1 Rule 0
• AIPS_BRIDGE_GROUP1_MEM_RULE1
  AIPS_BRIDGE_GROUP1_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 1 Rule 1
• AIPS_BRIDGE_GROUP2_MEM_RULE0
  AIPS_BRIDGE_GROUP2_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 2 Rule 0
• AIPS_BRIDGE_GROUP2_MEM_RULE1
  AIPS_BRIDGE_GROUP2_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 2 Memory Rule 1
• AIPS_BRIDGE_GROUP3_MEM_RULE0
  AIPS_BRIDGE_GROUP3_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 3 Rule 0
• AIPS_BRIDGE_GROUP3_MEM_RULE1
  AIPS_BRIDGE_GROUP3_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 3 Memory Rule 1
• AIPS_BRIDGE_GROUP3_MEM_RULE2
  AIPS_BRIDGE_GROUP3_MEM_RULE2 (rw) register accessor: AIPS Bridge Group 3 Rule 2
• AIPS_BRIDGE_GROUP3_MEM_RULE3
  AIPS_BRIDGE_GROUP3_MEM_RULE3 (rw) register accessor: AIPS Bridge Group 3 Rule 3
• AIPS_BRIDGE_GROUP4_MEM_RULE0
  AIPS_BRIDGE_GROUP4_MEM_RULE0 (rw) register accessor: AIPS Bridge Group 4 Rule 0
• AIPS_BRIDGE_GROUP4_MEM_RULE1
  AIPS_BRIDGE_GROUP4_MEM_RULE1 (rw) register accessor: AIPS Bridge Group 4 Rule 1
• AIPS_BRIDGE_GROUP4_MEM_RULE2
  AIPS_BRIDGE_GROUP4_MEM_RULE2 (rw) register accessor: AIPS Bridge Group 4 Rule 2
• AIPS_BRIDGE_GROUP4_MEM_RULE3
  AIPS_BRIDGE_GROUP4_MEM_RULE3 (rw) register accessor: AIPS Bridge Group 4 Rule 3
• APB_PERIPHERAL_GROUP0_MEM_RULE0
  APB_PERIPHERAL_GROUP0_MEM_RULE0 (rw) register accessor: APB Bridge Group 0 Memory Rule 0
• APB_PERIPHERAL_GROUP0_MEM_RULE1
  APB_PERIPHERAL_GROUP0_MEM_RULE1 (rw) register accessor: APB Bridge Group 0 Memory Rule 1
• APB_PERIPHERAL_GROUP0_MEM_RULE2
  APB_PERIPHERAL_GROUP0_MEM_RULE2 (rw) register accessor: APB Bridge Group 0 Rule 2
• APB_PERIPHERAL_GROUP0_MEM_RULE3
  APB_PERIPHERAL_GROUP0_MEM_RULE3 (rw) register accessor: APB Bridge Group 0 Memory Rule 3
• APB_PERIPHERAL_GROUP1_MEM_RULE0
  APB_PERIPHERAL_GROUP1_MEM_RULE0 (rw) register accessor: APB Bridge Group 1 Memory Rule 0
• APB_PERIPHERAL_GROUP1_MEM_RULE1
  APB_PERIPHERAL_GROUP1_MEM_RULE1 (rw) register accessor: APB Bridge Group 1 Memory Rule 1
• APB_PERIPHERAL_GROUP1_MEM_RULE2
  APB_PERIPHERAL_GROUP1_MEM_RULE2 (rw) register accessor: APB Bridge Group 1 Memory Rule 2
• CPU0_LOCK_REG
  CPU0_LOCK_REG (rw) register accessor: Miscellaneous CPU0 Control Signals
• CPU1_LOCK_REG
  CPU1_LOCK_REG (rw) register accessor: Miscellaneous CPU1 Control Signals
• FLASH00_MEM_RULE
  FLASH00_MEM_RULE (rw) register accessor: Flash Memory Rule
• FLASH01_MEM_RULE
  FLASH01_MEM_RULE (rw) register accessor: Flash Memory Rule
• FLASH02_MEM_RULE
  FLASH02_MEM_RULE (rw) register accessor: Flash Memory Rule
• FLASH03_MEM_RULE
  FLASH03_MEM_RULE (rw) register accessor: Flash Memory Rule
• FLEXSPI0_REGION0_MEM_RULE
  FLEXSPI0_REGION0_MEM_RULE (rw) register accessor: FLEXSPI0 Region 0 Memory Rule
• FLEXSPI0_REGION7_MEM_RULE
  FLEXSPI0_REGION7_MEM_RULE (rw) register accessor: FLEXSPI0 Region 7 Memory Rule
• MASTER_SEC_ANTI_POL_REG
  MASTER_SEC_ANTI_POL_REG (rw) register accessor: Master Secure Level
• MASTER_SEC_LEVEL
  MASTER_SEC_LEVEL (rw) register accessor: Master Secure Level
• MISC_CTRL_DP_REG
  MISC_CTRL_DP_REG (rw) register accessor: Secure Control Duplicate
• MISC_CTRL_REG
  MISC_CTRL_REG (rw) register accessor: Secure Control
• RAMA_MEM_RULE
  RAMA_MEM_RULE (rw) register accessor: RAMA Memory Rule 0
• RAMB_MEM_RULE
  RAMB_MEM_RULE (rw) register accessor: RAMB Memory Rule
• RAMC_MEM_RULE
  RAMC_MEM_RULE (rw) register accessor: RAMC Memory Rule
• RAMD_MEM_RULE
  RAMD_MEM_RULE (rw) register accessor: RAMD Memory Rule
• RAME_MEM_RULE
  RAME_MEM_RULE (rw) register accessor: RAME Memory Rule
• RAMF_MEM_RULE
  RAMF_MEM_RULE (rw) register accessor: RAMF Memory Rule
• RAMG_MEM_RULE
  RAMG_MEM_RULE (rw) register accessor: RAMG Memory Rule
• RAMH_MEM_RULE
  RAMH_MEM_RULE (rw) register accessor: RAMH Memory Rule
• RAMX_MEM_RULE
  RAMX_MEM_RULE (rw) register accessor: RAMX Memory Rule
• ROM_MEM_RULE
  ROM_MEM_RULE (rw) register accessor: ROM Memory Rule
• SEC_CPU1_INT_MASK0
  SEC_CPU1_INT_MASK0 (rw) register accessor: Secure Interrupt Mask 0 for CPU1
• SEC_CPU1_INT_MASK1
  SEC_CPU1_INT_MASK1 (rw) register accessor: Secure Interrupt Mask 1 for CPU1
• SEC_CPU1_INT_MASK2
  SEC_CPU1_INT_MASK2 (rw) register accessor: Secure Interrupt Mask 2 for CPU1
• SEC_CPU1_INT_MASK3
  SEC_CPU1_INT_MASK3 (rw) register accessor: Secure Interrupt Mask 3 for CPU1
• SEC_CPU1_INT_MASK4
  SEC_CPU1_INT_MASK4 (rw) register accessor: Secure Interrupt Mask 4 for CPU1
• SEC_GPIO_MASK
  SEC_GPIO_MASK (rw) register accessor: GPIO Mask for Port index
• SEC_GP_REG_LOCK
  SEC_GP_REG_LOCK (rw) register accessor: Secure Mask Lock
• SEC_VIO_ADDR
  SEC_VIO_ADDR (r) register accessor: Security Violation Address
• SEC_VIO_INFO_VALID
  SEC_VIO_INFO_VALID (rw) register accessor: Security Violation Info Validity for Address
• SEC_VIO_MISC_INFO
  SEC_VIO_MISC_INFO (r) register accessor: Security Violation Miscellaneous Information at Address