List of all items
Structs
- CBP
- CPUID
- CorePeripherals
- DCB
- DMA
- DWT
- FCR
- FLC
- FPB
- FPU
- GCR
- GPIO0
- I2C0
- I2C1
- ICC
- ITM
- MPU
- NVIC
- PWRSEQ
- Peripherals
- RTC
- SCB
- SIR
- SPI0
- SPI1
- SYST
- TMR0
- TMR1
- TMR2
- TPIU
- UART0
- UART1
- WDT0
- dma::RegisterBlock
- dma::ch::CH
- dma::ch::cfg::CFG_SPEC
- dma::ch::cnt::CNT_SPEC
- dma::ch::cnt_rld::CNT_RLD_SPEC
- dma::ch::dst::DST_SPEC
- dma::ch::dst_rld::DST_RLD_SPEC
- dma::ch::src::SRC_SPEC
- dma::ch::src_rld::SRC_RLD_SPEC
- dma::ch::stat::STAT_SPEC
- dma::int_en::INT_EN_SPEC
- dma::int_fl::INT_FL_SPEC
- fcr::RegisterBlock
- fcr::reg0::REG0_SPEC
- flc::RegisterBlock
- flc::actrl::ACTRL_SPEC
- flc::addr::ADDR_SPEC
- flc::clkdiv::CLKDIV_SPEC
- flc::ctrl::CTRL_SPEC
- flc::data::DATA_SPEC
- flc::intr::INTR_SPEC
- gcr::RegisterBlock
- gcr::clk_ctrl::CLK_CTRL_SPEC
- gcr::evten::EVTEN_SPEC
- gcr::mem_ctrl::MEM_CTRL_SPEC
- gcr::mem_zctrl::MEM_ZCTRL_SPEC
- gcr::pclk_dis0::PCLK_DIS0_SPEC
- gcr::pclk_dis1::PCLK_DIS1_SPEC
- gcr::pm::PM_SPEC
- gcr::rev::REV_SPEC
- gcr::rst0::RST0_SPEC
- gcr::rst1::RST1_SPEC
- gcr::scon::SCON_SPEC
- gcr::sys_ie::SYS_IE_SPEC
- gcr::sys_stat::SYS_STAT_SPEC
- generic::Reg
- gpio0::RegisterBlock
- gpio0::ds0::DS0_SPEC
- gpio0::ds1::DS1_SPEC
- gpio0::en0::EN0_SPEC
- gpio0::en0_clr::EN0_CLR_SPEC
- gpio0::en0_set::EN0_SET_SPEC
- gpio0::en1::EN1_SPEC
- gpio0::en1_clr::EN1_CLR_SPEC
- gpio0::en1_set::EN1_SET_SPEC
- gpio0::en2::EN2_SPEC
- gpio0::en2_clr::EN2_CLR_SPEC
- gpio0::en2_set::EN2_SET_SPEC
- gpio0::in_::IN_SPEC
- gpio0::int_clr::INT_CLR_SPEC
- gpio0::int_dual_edge::INT_DUAL_EDGE_SPEC
- gpio0::int_en::INT_EN_SPEC
- gpio0::int_en_clr::INT_EN_CLR_SPEC
- gpio0::int_en_set::INT_EN_SET_SPEC
- gpio0::int_mode::INT_MODE_SPEC
- gpio0::int_pol::INT_POL_SPEC
- gpio0::int_stat::INT_STAT_SPEC
- gpio0::is::IS_SPEC
- gpio0::out::OUT_SPEC
- gpio0::out_clr::OUT_CLR_SPEC
- gpio0::out_en::OUT_EN_SPEC
- gpio0::out_en_clr::OUT_EN_CLR_SPEC
- gpio0::out_en_set::OUT_EN_SET_SPEC
- gpio0::out_set::OUT_SET_SPEC
- gpio0::pad_cfg::PAD_CFG_SPEC
- gpio0::ps::PS_SPEC
- gpio0::sr::SR_SPEC
- gpio0::wake_en::WAKE_EN_SPEC
- gpio0::wake_en_clr::WAKE_EN_CLR_SPEC
- gpio0::wake_en_set::WAKE_EN_SET_SPEC
- i2c0::RegisterBlock
- i2c0::clkhi::CLKHI_SPEC
- i2c0::clklo::CLKLO_SPEC
- i2c0::ctrl0::CTRL0_SPEC
- i2c0::dma::DMA_SPEC
- i2c0::fifo::FIFO_SPEC
- i2c0::fifolen::FIFOLEN_SPEC
- i2c0::hs_clk::HS_CLK_SPEC
- i2c0::inten0::INTEN0_SPEC
- i2c0::inten1::INTEN1_SPEC
- i2c0::intfl0::INTFL0_SPEC
- i2c0::intfl1::INTFL1_SPEC
- i2c0::mstr_mode::MSTR_MODE_SPEC
- i2c0::rxctrl0::RXCTRL0_SPEC
- i2c0::rxctrl1::RXCTRL1_SPEC
- i2c0::sladdr::SLADDR_SPEC
- i2c0::status::STATUS_SPEC
- i2c0::timeout::TIMEOUT_SPEC
- i2c0::txctrl0::TXCTRL0_SPEC
- i2c0::txctrl1::TXCTRL1_SPEC
- icc::RegisterBlock
- icc::cache_ctrl::CACHE_CTRL_SPEC
- icc::cache_id::CACHE_ID_SPEC
- icc::invalidate::INVALIDATE_SPEC
- icc::mem_size::MEM_SIZE_SPEC
- pwrseq::RegisterBlock
- pwrseq::lp_ctrl::LP_CTRL_SPEC
- pwrseq::lp_wakefl::LP_WAKEFL_SPEC
- pwrseq::lpmemsd::LPMEMSD_SPEC
- pwrseq::lpwk_en::LPWK_EN_SPEC
- rtc::RegisterBlock
- rtc::ctrl::CTRL_SPEC
- rtc::oscctrl::OSCCTRL_SPEC
- rtc::ras::RAS_SPEC
- rtc::rssa::RSSA_SPEC
- rtc::sec::SEC_SPEC
- rtc::ssec::SSEC_SPEC
- rtc::trim::TRIM_SPEC
- sir::RegisterBlock
- sir::addr::ADDR_SPEC
- sir::status::STATUS_SPEC
- spi0::RegisterBlock
- spi0::clk_cfg::CLK_CFG_SPEC
- spi0::ctrl0::CTRL0_SPEC
- spi0::ctrl1::CTRL1_SPEC
- spi0::ctrl2::CTRL2_SPEC
- spi0::data::DATA_SPEC
- spi0::dma::DMA_SPEC
- spi0::int_en::INT_EN_SPEC
- spi0::int_fl::INT_FL_SPEC
- spi0::ss_time::SS_TIME_SPEC
- spi0::stat::STAT_SPEC
- spi0::wake_en::WAKE_EN_SPEC
- spi0::wake_fl::WAKE_FL_SPEC
- spi1::RegisterBlock
- spi1::brg::BRG_SPEC
- spi1::ctrl::CTRL_SPEC
- spi1::data::DATA_SPEC
- spi1::dma::DMA_SPEC
- spi1::i2s_ctrl::I2S_CTRL_SPEC
- spi1::int_fl::INT_FL_SPEC
- spi1::mode::MODE_SPEC
- tmr0::RegisterBlock
- tmr0::cmp::CMP_SPEC
- tmr0::cn::CN_SPEC
- tmr0::cnt::CNT_SPEC
- tmr0::intr::INTR_SPEC
- tmr0::pwm::PWM_SPEC
- uart0::RegisterBlock
- uart0::baud0::BAUD0_SPEC
- uart0::baud1::BAUD1_SPEC
- uart0::ctrl0::CTRL0_SPEC
- uart0::ctrl1::CTRL1_SPEC
- uart0::dma::DMA_SPEC
- uart0::fifo::FIFO_SPEC
- uart0::int_en::INT_EN_SPEC
- uart0::int_fl::INT_FL_SPEC
- uart0::stat::STAT_SPEC
- uart0::txfifo::TXFIFO_SPEC
- wdt0::RegisterBlock
- wdt0::ctrl::CTRL_SPEC
- wdt0::rst::RST_SPEC
Enums
- Interrupt
- dma::ch::cfg::BRST_A
- dma::ch::cfg::CHDIEN_A
- dma::ch::cfg::CHEN_A
- dma::ch::cfg::CTZIEN_A
- dma::ch::cfg::DSTINC_A
- dma::ch::cfg::DSTWD_A
- dma::ch::cfg::PRI_A
- dma::ch::cfg::PSSEL_A
- dma::ch::cfg::REQSEL_A
- dma::ch::cfg::REQWAIT_A
- dma::ch::cfg::RLDEN_A
- dma::ch::cfg::SRCINC_A
- dma::ch::cfg::SRCWD_A
- dma::ch::cfg::TOSEL_A
- dma::ch::cnt_rld::RLDEN_A
- dma::ch::stat::BUS_ERR_A
- dma::ch::stat::BUS_ERR_AW
- dma::ch::stat::CH_ST_A
- dma::ch::stat::CTZ_ST_A
- dma::ch::stat::CTZ_ST_AW
- dma::ch::stat::IPEND_A
- dma::ch::stat::RLD_ST_A
- dma::ch::stat::RLD_ST_AW
- dma::ch::stat::TO_ST_A
- dma::ch::stat::TO_ST_AW
- dma::int_en::CHIEN0_A
- dma::int_en::CHIEN1_A
- dma::int_en::CHIEN2_A
- dma::int_en::CHIEN3_A
- dma::int_fl::IPEND0_A
- dma::int_fl::IPEND1_A
- dma::int_fl::IPEND2_A
- dma::int_fl::IPEND3_A
- fcr::reg0::I2C0_SCL_FILTER_EN_A
- fcr::reg0::I2C0_SDA_FILTER_EN_A
- fcr::reg0::I2C1_SCL_FILTER_EN_A
- fcr::reg0::I2C1_SDA_FILTER_EN_A
- flc::ctrl::BUSY_A
- flc::ctrl::ERASE_CODE_A
- flc::ctrl::UNLOCK_CODE_A
- flc::ctrl::WIDTH_A
- flc::ctrl::WRITE_A
- flc::intr::ACCESS_FAIL_A
- flc::intr::DONE_A
- flc::intr::DONE_IE_A
- gcr::clk_ctrl::CLKRDY_A
- gcr::clk_ctrl::CLKSEL_A
- gcr::clk_ctrl::PSC_A
- gcr::clk_ctrl::X32K_EN_A
- gcr::clk_ctrl::X32K_RDY_A
- gcr::mem_ctrl::FWS_A
- gcr::mem_ctrl::ICACHE_RET_A
- gcr::mem_ctrl::RAM0_LS_A
- gcr::mem_ctrl::RAM1_LS_A
- gcr::mem_ctrl::RAM2_LS_A
- gcr::mem_ctrl::RAM3_LS_A
- gcr::mem_zctrl::ICACHE_ZERO_A
- gcr::mem_zctrl::SRAM_ZERO_A
- gcr::pclk_dis0::DMA_A
- gcr::pclk_dis0::GPIO0_A
- gcr::pclk_dis0::I2C0_A
- gcr::pclk_dis0::I2C1D_A
- gcr::pclk_dis0::SPI0_A
- gcr::pclk_dis0::SPI1_A
- gcr::pclk_dis0::TMR0_A
- gcr::pclk_dis0::TMR1_A
- gcr::pclk_dis0::TMR2_A
- gcr::pclk_dis0::UART0_A
- gcr::pclk_dis0::UART1_A
- gcr::pclk_dis1::FLC_A
- gcr::pclk_dis1::ICCD_A
- gcr::pm::GPIOWK_EN_A
- gcr::pm::HFIOPD_A
- gcr::pm::MODE_A
- gcr::pm::RTCWK_EN_A
- gcr::rst1::I2C1_A
- gcr::rst1::I2C1_AW
- gcr::scon::FLASH_PAGE_FLIP_A
- gcr::scon::FPU_DIS_A
- gcr::scon::ICC_FLUSH_A
- gcr::scon::SWD_DIS_A
- gcr::sys_stat::ICECLOCK_A
- gpio0::ds0::P0_A
- gpio0::ds0::P10_A
- gpio0::ds0::P11_A
- gpio0::ds0::P12_A
- gpio0::ds0::P13_A
- gpio0::ds0::P1_A
- gpio0::ds0::P2_A
- gpio0::ds0::P3_A
- gpio0::ds0::P4_A
- gpio0::ds0::P5_A
- gpio0::ds0::P6_A
- gpio0::ds0::P7_A
- gpio0::ds0::P8_A
- gpio0::ds0::P9_A
- gpio0::ds1::P0_A
- gpio0::ds1::P10_A
- gpio0::ds1::P11_A
- gpio0::ds1::P12_A
- gpio0::ds1::P13_A
- gpio0::ds1::P1_A
- gpio0::ds1::P2_A
- gpio0::ds1::P3_A
- gpio0::ds1::P4_A
- gpio0::ds1::P5_A
- gpio0::ds1::P6_A
- gpio0::ds1::P7_A
- gpio0::ds1::P8_A
- gpio0::ds1::P9_A
- gpio0::en0::P0_A
- gpio0::en0::P10_A
- gpio0::en0::P11_A
- gpio0::en0::P12_A
- gpio0::en0::P13_A
- gpio0::en0::P1_A
- gpio0::en0::P2_A
- gpio0::en0::P3_A
- gpio0::en0::P4_A
- gpio0::en0::P5_A
- gpio0::en0::P6_A
- gpio0::en0::P7_A
- gpio0::en0::P8_A
- gpio0::en0::P9_A
- gpio0::en0_clr::P0_AW
- gpio0::en0_clr::P10_AW
- gpio0::en0_clr::P11_AW
- gpio0::en0_clr::P12_AW
- gpio0::en0_clr::P13_AW
- gpio0::en0_clr::P1_AW
- gpio0::en0_clr::P2_AW
- gpio0::en0_clr::P3_AW
- gpio0::en0_clr::P4_AW
- gpio0::en0_clr::P5_AW
- gpio0::en0_clr::P6_AW
- gpio0::en0_clr::P7_AW
- gpio0::en0_clr::P8_AW
- gpio0::en0_clr::P9_AW
- gpio0::en0_set::P0_AW
- gpio0::en0_set::P10_AW
- gpio0::en0_set::P11_AW
- gpio0::en0_set::P12_AW
- gpio0::en0_set::P13_AW
- gpio0::en0_set::P1_AW
- gpio0::en0_set::P2_AW
- gpio0::en0_set::P3_AW
- gpio0::en0_set::P4_AW
- gpio0::en0_set::P5_AW
- gpio0::en0_set::P6_AW
- gpio0::en0_set::P7_AW
- gpio0::en0_set::P8_AW
- gpio0::en0_set::P9_AW
- gpio0::en1::P0_A
- gpio0::en1::P10_A
- gpio0::en1::P11_A
- gpio0::en1::P12_A
- gpio0::en1::P13_A
- gpio0::en1::P1_A
- gpio0::en1::P2_A
- gpio0::en1::P3_A
- gpio0::en1::P4_A
- gpio0::en1::P5_A
- gpio0::en1::P6_A
- gpio0::en1::P7_A
- gpio0::en1::P8_A
- gpio0::en1::P9_A
- gpio0::en1_clr::P0_AW
- gpio0::en1_clr::P10_AW
- gpio0::en1_clr::P11_AW
- gpio0::en1_clr::P12_AW
- gpio0::en1_clr::P13_AW
- gpio0::en1_clr::P1_AW
- gpio0::en1_clr::P2_AW
- gpio0::en1_clr::P3_AW
- gpio0::en1_clr::P4_AW
- gpio0::en1_clr::P5_AW
- gpio0::en1_clr::P6_AW
- gpio0::en1_clr::P7_AW
- gpio0::en1_clr::P8_AW
- gpio0::en1_clr::P9_AW
- gpio0::en1_set::P0_AW
- gpio0::en1_set::P10_AW
- gpio0::en1_set::P11_AW
- gpio0::en1_set::P12_AW
- gpio0::en1_set::P13_AW
- gpio0::en1_set::P1_AW
- gpio0::en1_set::P2_AW
- gpio0::en1_set::P3_AW
- gpio0::en1_set::P4_AW
- gpio0::en1_set::P5_AW
- gpio0::en1_set::P6_AW
- gpio0::en1_set::P7_AW
- gpio0::en1_set::P8_AW
- gpio0::en1_set::P9_AW
- gpio0::en2::P0_A
- gpio0::en2::P10_A
- gpio0::en2::P11_A
- gpio0::en2::P12_A
- gpio0::en2::P13_A
- gpio0::en2::P1_A
- gpio0::en2::P2_A
- gpio0::en2::P3_A
- gpio0::en2::P4_A
- gpio0::en2::P5_A
- gpio0::en2::P6_A
- gpio0::en2::P7_A
- gpio0::en2::P8_A
- gpio0::en2::P9_A
- gpio0::en2_clr::P0_AW
- gpio0::en2_clr::P10_AW
- gpio0::en2_clr::P11_AW
- gpio0::en2_clr::P12_AW
- gpio0::en2_clr::P13_AW
- gpio0::en2_clr::P1_AW
- gpio0::en2_clr::P2_AW
- gpio0::en2_clr::P3_AW
- gpio0::en2_clr::P4_AW
- gpio0::en2_clr::P5_AW
- gpio0::en2_clr::P6_AW
- gpio0::en2_clr::P7_AW
- gpio0::en2_clr::P8_AW
- gpio0::en2_clr::P9_AW
- gpio0::en2_set::P0_AW
- gpio0::en2_set::P10_AW
- gpio0::en2_set::P11_AW
- gpio0::en2_set::P12_AW
- gpio0::en2_set::P13_AW
- gpio0::en2_set::P1_AW
- gpio0::en2_set::P2_AW
- gpio0::en2_set::P3_AW
- gpio0::en2_set::P4_AW
- gpio0::en2_set::P5_AW
- gpio0::en2_set::P6_AW
- gpio0::en2_set::P7_AW
- gpio0::en2_set::P8_AW
- gpio0::en2_set::P9_AW
- gpio0::in_::P0_A
- gpio0::in_::P10_A
- gpio0::in_::P11_A
- gpio0::in_::P12_A
- gpio0::in_::P13_A
- gpio0::in_::P1_A
- gpio0::in_::P2_A
- gpio0::in_::P3_A
- gpio0::in_::P4_A
- gpio0::in_::P5_A
- gpio0::in_::P6_A
- gpio0::in_::P7_A
- gpio0::in_::P8_A
- gpio0::in_::P9_A
- gpio0::int_clr::P0_AW
- gpio0::int_clr::P10_AW
- gpio0::int_clr::P11_AW
- gpio0::int_clr::P12_AW
- gpio0::int_clr::P13_AW
- gpio0::int_clr::P1_AW
- gpio0::int_clr::P2_AW
- gpio0::int_clr::P3_AW
- gpio0::int_clr::P4_AW
- gpio0::int_clr::P5_AW
- gpio0::int_clr::P6_AW
- gpio0::int_clr::P7_AW
- gpio0::int_clr::P8_AW
- gpio0::int_clr::P9_AW
- gpio0::int_dual_edge::P0_A
- gpio0::int_dual_edge::P10_A
- gpio0::int_dual_edge::P11_A
- gpio0::int_dual_edge::P12_A
- gpio0::int_dual_edge::P13_A
- gpio0::int_dual_edge::P1_A
- gpio0::int_dual_edge::P2_A
- gpio0::int_dual_edge::P3_A
- gpio0::int_dual_edge::P4_A
- gpio0::int_dual_edge::P5_A
- gpio0::int_dual_edge::P6_A
- gpio0::int_dual_edge::P7_A
- gpio0::int_dual_edge::P8_A
- gpio0::int_dual_edge::P9_A
- gpio0::int_en::P0_A
- gpio0::int_en::P10_A
- gpio0::int_en::P11_A
- gpio0::int_en::P12_A
- gpio0::int_en::P13_A
- gpio0::int_en::P1_A
- gpio0::int_en::P2_A
- gpio0::int_en::P3_A
- gpio0::int_en::P4_A
- gpio0::int_en::P5_A
- gpio0::int_en::P6_A
- gpio0::int_en::P7_A
- gpio0::int_en::P8_A
- gpio0::int_en::P9_A
- gpio0::int_en_clr::P0_AW
- gpio0::int_en_clr::P10_AW
- gpio0::int_en_clr::P11_AW
- gpio0::int_en_clr::P12_AW
- gpio0::int_en_clr::P13_AW
- gpio0::int_en_clr::P1_AW
- gpio0::int_en_clr::P2_AW
- gpio0::int_en_clr::P3_AW
- gpio0::int_en_clr::P4_AW
- gpio0::int_en_clr::P5_AW
- gpio0::int_en_clr::P6_AW
- gpio0::int_en_clr::P7_AW
- gpio0::int_en_clr::P8_AW
- gpio0::int_en_clr::P9_AW
- gpio0::int_en_set::P0_AW
- gpio0::int_en_set::P10_AW
- gpio0::int_en_set::P11_AW
- gpio0::int_en_set::P12_AW
- gpio0::int_en_set::P13_AW
- gpio0::int_en_set::P1_AW
- gpio0::int_en_set::P2_AW
- gpio0::int_en_set::P3_AW
- gpio0::int_en_set::P4_AW
- gpio0::int_en_set::P5_AW
- gpio0::int_en_set::P6_AW
- gpio0::int_en_set::P7_AW
- gpio0::int_en_set::P8_AW
- gpio0::int_en_set::P9_AW
- gpio0::int_mode::P0_A
- gpio0::int_mode::P10_A
- gpio0::int_mode::P11_A
- gpio0::int_mode::P12_A
- gpio0::int_mode::P13_A
- gpio0::int_mode::P1_A
- gpio0::int_mode::P2_A
- gpio0::int_mode::P3_A
- gpio0::int_mode::P4_A
- gpio0::int_mode::P5_A
- gpio0::int_mode::P6_A
- gpio0::int_mode::P7_A
- gpio0::int_mode::P8_A
- gpio0::int_mode::P9_A
- gpio0::int_pol::P0_A
- gpio0::int_pol::P10_A
- gpio0::int_pol::P11_A
- gpio0::int_pol::P12_A
- gpio0::int_pol::P13_A
- gpio0::int_pol::P1_A
- gpio0::int_pol::P2_A
- gpio0::int_pol::P3_A
- gpio0::int_pol::P4_A
- gpio0::int_pol::P5_A
- gpio0::int_pol::P6_A
- gpio0::int_pol::P7_A
- gpio0::int_pol::P8_A
- gpio0::int_pol::P9_A
- gpio0::int_stat::P0_A
- gpio0::int_stat::P10_A
- gpio0::int_stat::P11_A
- gpio0::int_stat::P12_A
- gpio0::int_stat::P13_A
- gpio0::int_stat::P1_A
- gpio0::int_stat::P2_A
- gpio0::int_stat::P3_A
- gpio0::int_stat::P4_A
- gpio0::int_stat::P5_A
- gpio0::int_stat::P6_A
- gpio0::int_stat::P7_A
- gpio0::int_stat::P8_A
- gpio0::int_stat::P9_A
- gpio0::is::P0_A
- gpio0::is::P10_A
- gpio0::is::P11_A
- gpio0::is::P12_A
- gpio0::is::P13_A
- gpio0::is::P1_A
- gpio0::is::P2_A
- gpio0::is::P3_A
- gpio0::is::P4_A
- gpio0::is::P5_A
- gpio0::is::P6_A
- gpio0::is::P7_A
- gpio0::is::P8_A
- gpio0::is::P9_A
- gpio0::out::P0_A
- gpio0::out::P10_A
- gpio0::out::P11_A
- gpio0::out::P12_A
- gpio0::out::P13_A
- gpio0::out::P1_A
- gpio0::out::P2_A
- gpio0::out::P3_A
- gpio0::out::P4_A
- gpio0::out::P5_A
- gpio0::out::P6_A
- gpio0::out::P7_A
- gpio0::out::P8_A
- gpio0::out::P9_A
- gpio0::out_clr::P0_AW
- gpio0::out_clr::P10_AW
- gpio0::out_clr::P11_AW
- gpio0::out_clr::P12_AW
- gpio0::out_clr::P13_AW
- gpio0::out_clr::P1_AW
- gpio0::out_clr::P2_AW
- gpio0::out_clr::P3_AW
- gpio0::out_clr::P4_AW
- gpio0::out_clr::P5_AW
- gpio0::out_clr::P6_AW
- gpio0::out_clr::P7_AW
- gpio0::out_clr::P8_AW
- gpio0::out_clr::P9_AW
- gpio0::out_en::P0_A
- gpio0::out_en::P10_A
- gpio0::out_en::P11_A
- gpio0::out_en::P12_A
- gpio0::out_en::P13_A
- gpio0::out_en::P1_A
- gpio0::out_en::P2_A
- gpio0::out_en::P3_A
- gpio0::out_en::P4_A
- gpio0::out_en::P5_A
- gpio0::out_en::P6_A
- gpio0::out_en::P7_A
- gpio0::out_en::P8_A
- gpio0::out_en::P9_A
- gpio0::out_en_clr::P0_AW
- gpio0::out_en_clr::P10_AW
- gpio0::out_en_clr::P11_AW
- gpio0::out_en_clr::P12_AW
- gpio0::out_en_clr::P13_AW
- gpio0::out_en_clr::P1_AW
- gpio0::out_en_clr::P2_AW
- gpio0::out_en_clr::P3_AW
- gpio0::out_en_clr::P4_AW
- gpio0::out_en_clr::P5_AW
- gpio0::out_en_clr::P6_AW
- gpio0::out_en_clr::P7_AW
- gpio0::out_en_clr::P8_AW
- gpio0::out_en_clr::P9_AW
- gpio0::out_en_set::P0_AW
- gpio0::out_en_set::P10_AW
- gpio0::out_en_set::P11_AW
- gpio0::out_en_set::P12_AW
- gpio0::out_en_set::P13_AW
- gpio0::out_en_set::P1_AW
- gpio0::out_en_set::P2_AW
- gpio0::out_en_set::P3_AW
- gpio0::out_en_set::P4_AW
- gpio0::out_en_set::P5_AW
- gpio0::out_en_set::P6_AW
- gpio0::out_en_set::P7_AW
- gpio0::out_en_set::P8_AW
- gpio0::out_en_set::P9_AW
- gpio0::out_set::P0_AW
- gpio0::out_set::P10_AW
- gpio0::out_set::P11_AW
- gpio0::out_set::P12_AW
- gpio0::out_set::P13_AW
- gpio0::out_set::P1_AW
- gpio0::out_set::P2_AW
- gpio0::out_set::P3_AW
- gpio0::out_set::P4_AW
- gpio0::out_set::P5_AW
- gpio0::out_set::P6_AW
- gpio0::out_set::P7_AW
- gpio0::out_set::P8_AW
- gpio0::out_set::P9_AW
- gpio0::pad_cfg::P0_A
- gpio0::pad_cfg::P10_A
- gpio0::pad_cfg::P11_A
- gpio0::pad_cfg::P12_A
- gpio0::pad_cfg::P13_A
- gpio0::pad_cfg::P1_A
- gpio0::pad_cfg::P2_A
- gpio0::pad_cfg::P3_A
- gpio0::pad_cfg::P4_A
- gpio0::pad_cfg::P5_A
- gpio0::pad_cfg::P6_A
- gpio0::pad_cfg::P7_A
- gpio0::pad_cfg::P8_A
- gpio0::pad_cfg::P9_A
- gpio0::ps::P0_A
- gpio0::ps::P10_A
- gpio0::ps::P11_A
- gpio0::ps::P12_A
- gpio0::ps::P13_A
- gpio0::ps::P1_A
- gpio0::ps::P2_A
- gpio0::ps::P3_A
- gpio0::ps::P4_A
- gpio0::ps::P5_A
- gpio0::ps::P6_A
- gpio0::ps::P7_A
- gpio0::ps::P8_A
- gpio0::ps::P9_A
- gpio0::sr::P0_A
- gpio0::sr::P10_A
- gpio0::sr::P11_A
- gpio0::sr::P12_A
- gpio0::sr::P13_A
- gpio0::sr::P1_A
- gpio0::sr::P2_A
- gpio0::sr::P3_A
- gpio0::sr::P4_A
- gpio0::sr::P5_A
- gpio0::sr::P6_A
- gpio0::sr::P7_A
- gpio0::sr::P8_A
- gpio0::sr::P9_A
- gpio0::wake_en::P0_A
- gpio0::wake_en::P10_A
- gpio0::wake_en::P11_A
- gpio0::wake_en::P12_A
- gpio0::wake_en::P13_A
- gpio0::wake_en::P1_A
- gpio0::wake_en::P2_A
- gpio0::wake_en::P3_A
- gpio0::wake_en::P4_A
- gpio0::wake_en::P5_A
- gpio0::wake_en::P6_A
- gpio0::wake_en::P7_A
- gpio0::wake_en::P8_A
- gpio0::wake_en::P9_A
- gpio0::wake_en_clr::P0_AW
- gpio0::wake_en_clr::P10_AW
- gpio0::wake_en_clr::P11_AW
- gpio0::wake_en_clr::P12_AW
- gpio0::wake_en_clr::P13_AW
- gpio0::wake_en_clr::P1_AW
- gpio0::wake_en_clr::P2_AW
- gpio0::wake_en_clr::P3_AW
- gpio0::wake_en_clr::P4_AW
- gpio0::wake_en_clr::P5_AW
- gpio0::wake_en_clr::P6_AW
- gpio0::wake_en_clr::P7_AW
- gpio0::wake_en_clr::P8_AW
- gpio0::wake_en_clr::P9_AW
- gpio0::wake_en_set::P0_AW
- gpio0::wake_en_set::P10_AW
- gpio0::wake_en_set::P11_AW
- gpio0::wake_en_set::P12_AW
- gpio0::wake_en_set::P13_AW
- gpio0::wake_en_set::P1_AW
- gpio0::wake_en_set::P2_AW
- gpio0::wake_en_set::P3_AW
- gpio0::wake_en_set::P4_AW
- gpio0::wake_en_set::P5_AW
- gpio0::wake_en_set::P6_AW
- gpio0::wake_en_set::P7_AW
- gpio0::wake_en_set::P8_AW
- gpio0::wake_en_set::P9_AW
- i2c0::ctrl0::ACK_A
- i2c0::ctrl0::GCEN_A
- i2c0::ctrl0::HSMODE_A
- i2c0::ctrl0::I2CEN_A
- i2c0::ctrl0::IRXM_A
- i2c0::ctrl0::MST_A
- i2c0::ctrl0::READ_A
- i2c0::ctrl0::SCLO_A
- i2c0::ctrl0::SCL_PPM_A
- i2c0::ctrl0::SCL_STRD_A
- i2c0::ctrl0::SDAO_A
- i2c0::ctrl0::SWOE_A
- i2c0::dma::RXEN_A
- i2c0::dma::TXEN_A
- i2c0::inten0::ADRACKIE_A
- i2c0::inten0::ADRERIE_A
- i2c0::inten0::AMIE_A
- i2c0::inten0::ARBERIE_A
- i2c0::inten0::DATERIE_A
- i2c0::inten0::DNRERIE_A
- i2c0::inten0::DONEIE_A
- i2c0::inten0::GCIE_A
- i2c0::inten0::IRXMIE_A
- i2c0::inten0::RXTHIE_A
- i2c0::inten0::STOPERIE_A
- i2c0::inten0::STOPIE_A
- i2c0::inten0::STRTERIE_A
- i2c0::inten0::TOERIE_A
- i2c0::inten0::TXLOIE_A
- i2c0::inten0::TXTHIE_A
- i2c0::inten1::RXOFIE_A
- i2c0::inten1::TXUFIE_A
- i2c0::intfl0::ADRACKI_A
- i2c0::intfl0::ADRERI_A
- i2c0::intfl0::AMI_A
- i2c0::intfl0::ARBERI_A
- i2c0::intfl0::DATERI_A
- i2c0::intfl0::DNRERI_A
- i2c0::intfl0::DONEI_A
- i2c0::intfl0::GCI_A
- i2c0::intfl0::IRXMI_A
- i2c0::intfl0::RXTHI_A
- i2c0::intfl0::STOPERI_A
- i2c0::intfl0::STOPI_A
- i2c0::intfl0::STRTERI_A
- i2c0::intfl0::TOERI_A
- i2c0::intfl0::TXTHI_A
- i2c0::intfl1::RXOFI_A
- i2c0::intfl1::TXUFI_A
- i2c0::mstr_mode::SEA_A
- i2c0::rxctrl0::DNR_A
- i2c0::rxctrl0::RXFSH_A
- i2c0::sladdr::EA_A
- i2c0::status::BUSY_A
- i2c0::status::CKMD_A
- i2c0::status::RXE_A
- i2c0::status::RXF_A
- i2c0::status::STAT_A
- i2c0::status::TXE_A
- i2c0::status::TXF_A
- i2c0::txctrl0::TXFSH_A
- i2c0::txctrl0::TX_READY_MODE_A
- i2c0::txctrl1::FLSH_GCADDR_DIS_A
- i2c0::txctrl1::FLSH_NACK_DIS_A
- i2c0::txctrl1::FLSH_SLADDR_DIS_A
- i2c0::txctrl1::TXLAST_A
- icc::cache_ctrl::ENABLED_A
- icc::cache_ctrl::READY_A
- pwrseq::lp_ctrl::BG_OFF_A
- pwrseq::lp_ctrl::FAST_WK_EN_A
- pwrseq::lp_ctrl::LDO_DIS_A
- pwrseq::lp_ctrl::OVR_A
- pwrseq::lp_ctrl::RAMRET_SEL0_A
- pwrseq::lp_ctrl::RAMRET_SEL1_A
- pwrseq::lp_ctrl::RAMRET_SEL2_A
- pwrseq::lp_ctrl::RAMRET_SEL3_A
- pwrseq::lp_ctrl::RETREG_EN_A
- pwrseq::lp_ctrl::VCORE_DET_BYPASS_A
- pwrseq::lp_ctrl::VCORE_POR_DIS_A
- pwrseq::lp_ctrl::VCORE_SVM_DIS_A
- pwrseq::lp_ctrl::VDDIO_POR_DIS_A
- pwrseq::lpmemsd::SRAM0_OFF_A
- pwrseq::lpmemsd::SRAM1_OFF_A
- pwrseq::lpmemsd::SRAM2_OFF_A
- pwrseq::lpmemsd::SRAM3_OFF_A
- rtc::ctrl::ADE_A
- rtc::ctrl::ALDF_A
- rtc::ctrl::ALSF_A
- rtc::ctrl::ASE_A
- rtc::ctrl::BUSY_A
- rtc::ctrl::FT_A
- rtc::ctrl::RDYE_A
- rtc::ctrl::RDY_A
- rtc::ctrl::RTCE_A
- rtc::ctrl::SQE_A
- rtc::ctrl::WE_A
- rtc::ctrl::X32KMD_A
- rtc::oscctrl::IBIAS_SEL_A
- sir::status::CFG_ERR_A
- sir::status::CFG_VALID_A
- spi0::clk_cfg::HI_A
- spi0::clk_cfg::LO_A
- spi0::ctrl0::MM_EN_A
- spi0::ctrl0::SPI_EN_A
- spi0::ctrl0::SS_CTRL_A
- spi0::ctrl0::SS_IO_A
- spi0::ctrl0::SS_SEL_A
- spi0::ctrl0::START_A
- spi0::ctrl2::CLK_PHA_A
- spi0::ctrl2::CLK_POL_A
- spi0::ctrl2::DATA_WIDTH_A
- spi0::ctrl2::NUM_BITS_A
- spi0::ctrl2::SS_POL_A
- spi0::ctrl2::THREE_WIRE_A
- spi0::dma::RX_DMA_EN_A
- spi0::dma::RX_FIFO_CLEAR_A
- spi0::dma::RX_FIFO_EN_A
- spi0::dma::TX_DMA_EN_A
- spi0::dma::TX_FIFO_CLEAR_A
- spi0::dma::TX_FIFO_EN_A
- spi0::int_en::ABORT_A
- spi0::int_en::FAULT_A
- spi0::int_en::M_DONE_A
- spi0::int_en::RX_FULL_A
- spi0::int_en::RX_LEVEL_A
- spi0::int_en::RX_OVR_A
- spi0::int_en::RX_UND_A
- spi0::int_en::SSA_A
- spi0::int_en::SSD_A
- spi0::int_en::TX_EMPTY_A
- spi0::int_en::TX_LEVEL_A
- spi0::int_en::TX_OVR_A
- spi0::int_en::TX_UND_A
- spi0::int_fl::ABORT_A
- spi0::int_fl::M_DONE_A
- spi0::int_fl::RX_FULL_A
- spi0::int_fl::RX_LEVEL_A
- spi0::int_fl::RX_OVR_A
- spi0::int_fl::RX_UND_A
- spi0::int_fl::SSA_A
- spi0::int_fl::SSD_A
- spi0::int_fl::TX_EMPTY_A
- spi0::int_fl::TX_LEVEL_A
- spi0::int_fl::TX_OVR_A
- spi0::int_fl::TX_UND_A
- spi0::stat::BUSY_A
- spi0::wake_en::RX_FULL_A
- spi0::wake_en::RX_LEVEL_A
- spi0::wake_en::TX_EMPTY_A
- spi0::wake_en::TX_LEVEL_A
- spi0::wake_fl::RX_FULL_A
- spi0::wake_fl::RX_LEVEL_A
- spi0::wake_fl::TX_EMPTY_A
- spi0::wake_fl::TX_LEVEL_A
- spi1::ctrl::BIRQ_A
- spi1::ctrl::CLKPOL_A
- spi1::ctrl::ENABLED_A
- spi1::ctrl::IRQE_A
- spi1::ctrl::MMEN_A
- spi1::ctrl::PHASE_A
- spi1::ctrl::STR_A
- spi1::ctrl::WOR_A
- spi1::dma::RX_DMA_EN_A
- spi1::dma::RX_FIFO_CLR_A
- spi1::dma::RX_FIFO_LVL_A
- spi1::dma::TX_DMA_EN_A
- spi1::dma::TX_FIFO_CLR_AW
- spi1::dma::TX_FIFO_LVL_A
- spi1::i2s_ctrl::I2S_EN_A
- spi1::i2s_ctrl::I2S_LJ_A
- spi1::i2s_ctrl::I2S_MONO_A
- spi1::i2s_ctrl::I2S_MUTE_A
- spi1::i2s_ctrl::I2S_PAUSE_A
- spi1::int_fl::ABT_A
- spi1::int_fl::COL_A
- spi1::int_fl::IRQ_A
- spi1::int_fl::ROVR_A
- spi1::int_fl::SLAS_A
- spi1::int_fl::TOVR_A
- spi1::int_fl::TUND_A
- spi1::int_fl::TXST_A
- spi1::mode::NUMBITS_A
- spi1::mode::SSV_A
- spi1::mode::SS_IO_A
- spi1::mode::TX_LJ_A
- tmr0::cn::PRES_A
- tmr0::cn::TMODE_A
- uart0::baud0::CLKDIV_A
- uart0::ctrl0::BITACC_A
- uart0::ctrl0::BREAK_A
- uart0::ctrl0::CLK_SEL_A
- uart0::ctrl0::ENABLED_A
- uart0::ctrl0::FLOWPOL_A
- uart0::ctrl0::FLOW_A
- uart0::ctrl0::NULLMOD_A
- uart0::ctrl0::PARITY_EN_A
- uart0::ctrl0::PARITY_LVL_A
- uart0::ctrl0::PARITY_MODE_A
- uart0::ctrl0::SIZE_A
- uart0::ctrl0::STOP_A
- uart0::dma::RXDMA_EN_A
- uart0::dma::TXDMA_EN_A
- wdt0::ctrl::INT_EN_A
- wdt0::ctrl::INT_FLAG_A
- wdt0::ctrl::INT_PERIOD_A
- wdt0::ctrl::RST_EN_A
- wdt0::ctrl::RST_FLAG_A
- wdt0::ctrl::RST_PERIOD_A
- wdt0::ctrl::WDT_EN_A
- wdt0::rst::WDT_RST_AW
Traits
- generic::FieldSpec
- generic::RawReg
- generic::Readable
- generic::RegisterSpec
- generic::Resettable
- generic::Writable
Type Aliases
- dma::INT_EN
- dma::INT_FL
- dma::ch::CFG
- dma::ch::CNT
- dma::ch::CNT_RLD
- dma::ch::DST
- dma::ch::DST_RLD
- dma::ch::SRC
- dma::ch::SRC_RLD
- dma::ch::STAT
- dma::ch::cfg::BRST_R
- dma::ch::cfg::BRST_W
- dma::ch::cfg::CHDIEN_R
- dma::ch::cfg::CHDIEN_W
- dma::ch::cfg::CHEN_R
- dma::ch::cfg::CHEN_W
- dma::ch::cfg::CTZIEN_R
- dma::ch::cfg::CTZIEN_W
- dma::ch::cfg::DSTINC_R
- dma::ch::cfg::DSTINC_W
- dma::ch::cfg::DSTWD_R
- dma::ch::cfg::DSTWD_W
- dma::ch::cfg::PRI_R
- dma::ch::cfg::PRI_W
- dma::ch::cfg::PSSEL_R
- dma::ch::cfg::PSSEL_W
- dma::ch::cfg::R
- dma::ch::cfg::REQSEL_R
- dma::ch::cfg::REQSEL_W
- dma::ch::cfg::REQWAIT_R
- dma::ch::cfg::REQWAIT_W
- dma::ch::cfg::RLDEN_R
- dma::ch::cfg::RLDEN_W
- dma::ch::cfg::SRCINC_R
- dma::ch::cfg::SRCINC_W
- dma::ch::cfg::SRCWD_R
- dma::ch::cfg::SRCWD_W
- dma::ch::cfg::TOSEL_R
- dma::ch::cfg::TOSEL_W
- dma::ch::cfg::W
- dma::ch::cnt::CNT_R
- dma::ch::cnt::CNT_W
- dma::ch::cnt::R
- dma::ch::cnt::W
- dma::ch::cnt_rld::CNT_RLD_R
- dma::ch::cnt_rld::CNT_RLD_W
- dma::ch::cnt_rld::R
- dma::ch::cnt_rld::RLDEN_R
- dma::ch::cnt_rld::RLDEN_W
- dma::ch::cnt_rld::W
- dma::ch::dst::DST_R
- dma::ch::dst::DST_W
- dma::ch::dst::R
- dma::ch::dst::W
- dma::ch::dst_rld::DST_RLD_R
- dma::ch::dst_rld::DST_RLD_W
- dma::ch::dst_rld::R
- dma::ch::dst_rld::W
- dma::ch::src::R
- dma::ch::src::SRC_R
- dma::ch::src::SRC_W
- dma::ch::src::W
- dma::ch::src_rld::R
- dma::ch::src_rld::SRC_RLD_R
- dma::ch::src_rld::SRC_RLD_W
- dma::ch::src_rld::W
- dma::ch::stat::BUS_ERR_R
- dma::ch::stat::BUS_ERR_W
- dma::ch::stat::CH_ST_R
- dma::ch::stat::CTZ_ST_R
- dma::ch::stat::CTZ_ST_W
- dma::ch::stat::IPEND_R
- dma::ch::stat::R
- dma::ch::stat::RLD_ST_R
- dma::ch::stat::RLD_ST_W
- dma::ch::stat::TO_ST_R
- dma::ch::stat::TO_ST_W
- dma::ch::stat::W
- dma::int_en::CHIEN0_R
- dma::int_en::CHIEN0_W
- dma::int_en::CHIEN1_R
- dma::int_en::CHIEN1_W
- dma::int_en::CHIEN2_R
- dma::int_en::CHIEN2_W
- dma::int_en::CHIEN3_R
- dma::int_en::CHIEN3_W
- dma::int_en::R
- dma::int_en::W
- dma::int_fl::IPEND0_R
- dma::int_fl::IPEND1_R
- dma::int_fl::IPEND2_R
- dma::int_fl::IPEND3_R
- dma::int_fl::R
- fcr::REG0
- fcr::reg0::I2C0_SCL_FILTER_EN_R
- fcr::reg0::I2C0_SCL_FILTER_EN_W
- fcr::reg0::I2C0_SDA_FILTER_EN_R
- fcr::reg0::I2C0_SDA_FILTER_EN_W
- fcr::reg0::I2C1_SCL_FILTER_EN_R
- fcr::reg0::I2C1_SCL_FILTER_EN_W
- fcr::reg0::I2C1_SDA_FILTER_EN_R
- fcr::reg0::I2C1_SDA_FILTER_EN_W
- fcr::reg0::R
- fcr::reg0::W
- flc::ACTRL
- flc::ADDR
- flc::CLKDIV
- flc::CTRL
- flc::DATA
- flc::INTR
- flc::actrl::ACTRL_W
- flc::actrl::W
- flc::addr::ADDR_R
- flc::addr::ADDR_W
- flc::addr::R
- flc::addr::W
- flc::clkdiv::CLKDIV_R
- flc::clkdiv::CLKDIV_W
- flc::clkdiv::R
- flc::clkdiv::W
- flc::ctrl::BUSY_R
- flc::ctrl::ERASE_CODE_R
- flc::ctrl::ERASE_CODE_W
- flc::ctrl::LVE_R
- flc::ctrl::LVE_W
- flc::ctrl::R
- flc::ctrl::UNLOCK_CODE_R
- flc::ctrl::UNLOCK_CODE_W
- flc::ctrl::W
- flc::ctrl::WIDTH_R
- flc::ctrl::WIDTH_W
- flc::ctrl::WRITE_R
- flc::ctrl::WRITE_W
- flc::data::DATA_R
- flc::data::DATA_W
- flc::data::R
- flc::data::W
- flc::intr::ACCESS_FAIL_R
- flc::intr::ACCESS_FAIL_W
- flc::intr::DONE_IE_R
- flc::intr::DONE_IE_W
- flc::intr::DONE_R
- flc::intr::DONE_W
- flc::intr::R
- flc::intr::W
- gcr::CLK_CTRL
- gcr::EVTEN
- gcr::MEM_CTRL
- gcr::MEM_ZCTRL
- gcr::PCLK_DIS0
- gcr::PCLK_DIS1
- gcr::PM
- gcr::REV
- gcr::RST0
- gcr::RST1
- gcr::SCON
- gcr::SYS_IE
- gcr::SYS_STAT
- gcr::clk_ctrl::CLKRDY_R
- gcr::clk_ctrl::CLKSEL_R
- gcr::clk_ctrl::CLKSEL_W
- gcr::clk_ctrl::PSC_R
- gcr::clk_ctrl::PSC_W
- gcr::clk_ctrl::R
- gcr::clk_ctrl::W
- gcr::clk_ctrl::X32K_EN_R
- gcr::clk_ctrl::X32K_EN_W
- gcr::clk_ctrl::X32K_RDY_R
- gcr::evten::DMAEVENT_R
- gcr::evten::DMAEVENT_W
- gcr::evten::R
- gcr::evten::RX_EVT_R
- gcr::evten::RX_EVT_W
- gcr::evten::W
- gcr::mem_ctrl::FWS_R
- gcr::mem_ctrl::FWS_W
- gcr::mem_ctrl::ICACHE_RET_R
- gcr::mem_ctrl::ICACHE_RET_W
- gcr::mem_ctrl::R
- gcr::mem_ctrl::RAM0_LS_R
- gcr::mem_ctrl::RAM0_LS_W
- gcr::mem_ctrl::RAM1_LS_R
- gcr::mem_ctrl::RAM1_LS_W
- gcr::mem_ctrl::RAM2_LS_R
- gcr::mem_ctrl::RAM2_LS_W
- gcr::mem_ctrl::RAM3_LS_R
- gcr::mem_ctrl::RAM3_LS_W
- gcr::mem_ctrl::W
- gcr::mem_zctrl::ICACHE_ZERO_R
- gcr::mem_zctrl::ICACHE_ZERO_W
- gcr::mem_zctrl::R
- gcr::mem_zctrl::SRAM_ZERO_R
- gcr::mem_zctrl::SRAM_ZERO_W
- gcr::mem_zctrl::W
- gcr::pclk_dis0::DMA_R
- gcr::pclk_dis0::DMA_W
- gcr::pclk_dis0::GPIO0_R
- gcr::pclk_dis0::GPIO0_W
- gcr::pclk_dis0::I2C0_R
- gcr::pclk_dis0::I2C0_W
- gcr::pclk_dis0::I2C1D_R
- gcr::pclk_dis0::I2C1D_W
- gcr::pclk_dis0::R
- gcr::pclk_dis0::SPI0_R
- gcr::pclk_dis0::SPI0_W
- gcr::pclk_dis0::SPI1_R
- gcr::pclk_dis0::SPI1_W
- gcr::pclk_dis0::TMR0_R
- gcr::pclk_dis0::TMR0_W
- gcr::pclk_dis0::TMR1_R
- gcr::pclk_dis0::TMR1_W
- gcr::pclk_dis0::TMR2_R
- gcr::pclk_dis0::TMR2_W
- gcr::pclk_dis0::UART0_R
- gcr::pclk_dis0::UART0_W
- gcr::pclk_dis0::UART1_R
- gcr::pclk_dis0::UART1_W
- gcr::pclk_dis0::W
- gcr::pclk_dis1::FLC_R
- gcr::pclk_dis1::FLC_W
- gcr::pclk_dis1::ICCD_R
- gcr::pclk_dis1::ICCD_W
- gcr::pclk_dis1::R
- gcr::pclk_dis1::W
- gcr::pm::GPIOWK_EN_R
- gcr::pm::GPIOWK_EN_W
- gcr::pm::HFIOPD_R
- gcr::pm::HFIOPD_W
- gcr::pm::MODE_R
- gcr::pm::MODE_W
- gcr::pm::R
- gcr::pm::RTCWK_EN_R
- gcr::pm::RTCWK_EN_W
- gcr::pm::W
- gcr::rev::R
- gcr::rev::REVISION_R
- gcr::rst0::DMA_R
- gcr::rst0::DMA_W
- gcr::rst0::GPIO0_R
- gcr::rst0::GPIO0_W
- gcr::rst0::I2C0_R
- gcr::rst0::I2C0_W
- gcr::rst0::PERIPH_R
- gcr::rst0::PERIPH_W
- gcr::rst0::R
- gcr::rst0::RTC_R
- gcr::rst0::RTC_W
- gcr::rst0::SOFT_R
- gcr::rst0::SOFT_W
- gcr::rst0::SPI0_R
- gcr::rst0::SPI0_W
- gcr::rst0::SPI1_R
- gcr::rst0::SPI1_W
- gcr::rst0::SYSTEM_R
- gcr::rst0::SYSTEM_W
- gcr::rst0::TMR0_R
- gcr::rst0::TMR0_W
- gcr::rst0::TMR1_R
- gcr::rst0::TMR1_W
- gcr::rst0::TMR2_R
- gcr::rst0::TMR2_W
- gcr::rst0::UART0_R
- gcr::rst0::UART0_W
- gcr::rst0::UART1_R
- gcr::rst0::UART1_W
- gcr::rst0::W
- gcr::rst0::WDT0_R
- gcr::rst0::WDT0_W
- gcr::rst1::I2C1_R
- gcr::rst1::I2C1_W
- gcr::rst1::R
- gcr::rst1::W
- gcr::scon::FLASH_PAGE_FLIP_R
- gcr::scon::FLASH_PAGE_FLIP_W
- gcr::scon::FPU_DIS_R
- gcr::scon::FPU_DIS_W
- gcr::scon::ICC_FLUSH_R
- gcr::scon::ICC_FLUSH_W
- gcr::scon::R
- gcr::scon::SWD_DIS_R
- gcr::scon::SWD_DIS_W
- gcr::scon::W
- gcr::sys_ie::ICEULIE_R
- gcr::sys_ie::ICEULIE_W
- gcr::sys_ie::R
- gcr::sys_ie::W
- gcr::sys_stat::ICECLOCK_R
- gcr::sys_stat::ICECLOCK_W
- gcr::sys_stat::R
- gcr::sys_stat::W
- generic::BitReader
- generic::BitWriter
- generic::BitWriter0C
- generic::BitWriter0S
- generic::BitWriter0T
- generic::BitWriter1C
- generic::BitWriter1S
- generic::BitWriter1T
- generic::FieldReader
- generic::FieldWriter
- generic::FieldWriterSafe
- generic::R
- generic::W
- gpio0::DS0
- gpio0::DS1
- gpio0::EN0
- gpio0::EN0_CLR
- gpio0::EN0_SET
- gpio0::EN1
- gpio0::EN1_CLR
- gpio0::EN1_SET
- gpio0::EN2
- gpio0::EN2_CLR
- gpio0::EN2_SET
- gpio0::IN
- gpio0::INT_CLR
- gpio0::INT_DUAL_EDGE
- gpio0::INT_EN
- gpio0::INT_EN_CLR
- gpio0::INT_EN_SET
- gpio0::INT_MODE
- gpio0::INT_POL
- gpio0::INT_STAT
- gpio0::IS
- gpio0::OUT
- gpio0::OUT_CLR
- gpio0::OUT_EN
- gpio0::OUT_EN_CLR
- gpio0::OUT_EN_SET
- gpio0::OUT_SET
- gpio0::PAD_CFG
- gpio0::PS
- gpio0::SR
- gpio0::WAKE_EN
- gpio0::WAKE_EN_CLR
- gpio0::WAKE_EN_SET
- gpio0::ds0::P0_R
- gpio0::ds0::P0_W
- gpio0::ds0::P10_R
- gpio0::ds0::P10_W
- gpio0::ds0::P11_R
- gpio0::ds0::P11_W
- gpio0::ds0::P12_R
- gpio0::ds0::P12_W
- gpio0::ds0::P13_R
- gpio0::ds0::P13_W
- gpio0::ds0::P1_R
- gpio0::ds0::P1_W
- gpio0::ds0::P2_R
- gpio0::ds0::P2_W
- gpio0::ds0::P3_R
- gpio0::ds0::P3_W
- gpio0::ds0::P4_R
- gpio0::ds0::P4_W
- gpio0::ds0::P5_R
- gpio0::ds0::P5_W
- gpio0::ds0::P6_R
- gpio0::ds0::P6_W
- gpio0::ds0::P7_R
- gpio0::ds0::P7_W
- gpio0::ds0::P8_R
- gpio0::ds0::P8_W
- gpio0::ds0::P9_R
- gpio0::ds0::P9_W
- gpio0::ds0::R
- gpio0::ds0::W
- gpio0::ds1::P0_R
- gpio0::ds1::P0_W
- gpio0::ds1::P10_R
- gpio0::ds1::P10_W
- gpio0::ds1::P11_R
- gpio0::ds1::P11_W
- gpio0::ds1::P12_R
- gpio0::ds1::P12_W
- gpio0::ds1::P13_R
- gpio0::ds1::P13_W
- gpio0::ds1::P1_R
- gpio0::ds1::P1_W
- gpio0::ds1::P2_R
- gpio0::ds1::P2_W
- gpio0::ds1::P3_R
- gpio0::ds1::P3_W
- gpio0::ds1::P4_R
- gpio0::ds1::P4_W
- gpio0::ds1::P5_R
- gpio0::ds1::P5_W
- gpio0::ds1::P6_R
- gpio0::ds1::P6_W
- gpio0::ds1::P7_R
- gpio0::ds1::P7_W
- gpio0::ds1::P8_R
- gpio0::ds1::P8_W
- gpio0::ds1::P9_R
- gpio0::ds1::P9_W
- gpio0::ds1::R
- gpio0::ds1::W
- gpio0::en0::P0_R
- gpio0::en0::P0_W
- gpio0::en0::P10_R
- gpio0::en0::P10_W
- gpio0::en0::P11_R
- gpio0::en0::P11_W
- gpio0::en0::P12_R
- gpio0::en0::P12_W
- gpio0::en0::P13_R
- gpio0::en0::P13_W
- gpio0::en0::P1_R
- gpio0::en0::P1_W
- gpio0::en0::P2_R
- gpio0::en0::P2_W
- gpio0::en0::P3_R
- gpio0::en0::P3_W
- gpio0::en0::P4_R
- gpio0::en0::P4_W
- gpio0::en0::P5_R
- gpio0::en0::P5_W
- gpio0::en0::P6_R
- gpio0::en0::P6_W
- gpio0::en0::P7_R
- gpio0::en0::P7_W
- gpio0::en0::P8_R
- gpio0::en0::P8_W
- gpio0::en0::P9_R
- gpio0::en0::P9_W
- gpio0::en0::R
- gpio0::en0::W
- gpio0::en0_clr::P0_W
- gpio0::en0_clr::P10_W
- gpio0::en0_clr::P11_W
- gpio0::en0_clr::P12_W
- gpio0::en0_clr::P13_W
- gpio0::en0_clr::P1_W
- gpio0::en0_clr::P2_W
- gpio0::en0_clr::P3_W
- gpio0::en0_clr::P4_W
- gpio0::en0_clr::P5_W
- gpio0::en0_clr::P6_W
- gpio0::en0_clr::P7_W
- gpio0::en0_clr::P8_W
- gpio0::en0_clr::P9_W
- gpio0::en0_clr::W
- gpio0::en0_set::P0_W
- gpio0::en0_set::P10_W
- gpio0::en0_set::P11_W
- gpio0::en0_set::P12_W
- gpio0::en0_set::P13_W
- gpio0::en0_set::P1_W
- gpio0::en0_set::P2_W
- gpio0::en0_set::P3_W
- gpio0::en0_set::P4_W
- gpio0::en0_set::P5_W
- gpio0::en0_set::P6_W
- gpio0::en0_set::P7_W
- gpio0::en0_set::P8_W
- gpio0::en0_set::P9_W
- gpio0::en0_set::W
- gpio0::en1::P0_R
- gpio0::en1::P0_W
- gpio0::en1::P10_R
- gpio0::en1::P10_W
- gpio0::en1::P11_R
- gpio0::en1::P11_W
- gpio0::en1::P12_R
- gpio0::en1::P12_W
- gpio0::en1::P13_R
- gpio0::en1::P13_W
- gpio0::en1::P1_R
- gpio0::en1::P1_W
- gpio0::en1::P2_R
- gpio0::en1::P2_W
- gpio0::en1::P3_R
- gpio0::en1::P3_W
- gpio0::en1::P4_R
- gpio0::en1::P4_W
- gpio0::en1::P5_R
- gpio0::en1::P5_W
- gpio0::en1::P6_R
- gpio0::en1::P6_W
- gpio0::en1::P7_R
- gpio0::en1::P7_W
- gpio0::en1::P8_R
- gpio0::en1::P8_W
- gpio0::en1::P9_R
- gpio0::en1::P9_W
- gpio0::en1::R
- gpio0::en1::W
- gpio0::en1_clr::P0_W
- gpio0::en1_clr::P10_W
- gpio0::en1_clr::P11_W
- gpio0::en1_clr::P12_W
- gpio0::en1_clr::P13_W
- gpio0::en1_clr::P1_W
- gpio0::en1_clr::P2_W
- gpio0::en1_clr::P3_W
- gpio0::en1_clr::P4_W
- gpio0::en1_clr::P5_W
- gpio0::en1_clr::P6_W
- gpio0::en1_clr::P7_W
- gpio0::en1_clr::P8_W
- gpio0::en1_clr::P9_W
- gpio0::en1_clr::W
- gpio0::en1_set::P0_W
- gpio0::en1_set::P10_W
- gpio0::en1_set::P11_W
- gpio0::en1_set::P12_W
- gpio0::en1_set::P13_W
- gpio0::en1_set::P1_W
- gpio0::en1_set::P2_W
- gpio0::en1_set::P3_W
- gpio0::en1_set::P4_W
- gpio0::en1_set::P5_W
- gpio0::en1_set::P6_W
- gpio0::en1_set::P7_W
- gpio0::en1_set::P8_W
- gpio0::en1_set::P9_W
- gpio0::en1_set::W
- gpio0::en2::P0_R
- gpio0::en2::P0_W
- gpio0::en2::P10_R
- gpio0::en2::P10_W
- gpio0::en2::P11_R
- gpio0::en2::P11_W
- gpio0::en2::P12_R
- gpio0::en2::P12_W
- gpio0::en2::P13_R
- gpio0::en2::P13_W
- gpio0::en2::P1_R
- gpio0::en2::P1_W
- gpio0::en2::P2_R
- gpio0::en2::P2_W
- gpio0::en2::P3_R
- gpio0::en2::P3_W
- gpio0::en2::P4_R
- gpio0::en2::P4_W
- gpio0::en2::P5_R
- gpio0::en2::P5_W
- gpio0::en2::P6_R
- gpio0::en2::P6_W
- gpio0::en2::P7_R
- gpio0::en2::P7_W
- gpio0::en2::P8_R
- gpio0::en2::P8_W
- gpio0::en2::P9_R
- gpio0::en2::P9_W
- gpio0::en2::R
- gpio0::en2::W
- gpio0::en2_clr::P0_W
- gpio0::en2_clr::P10_W
- gpio0::en2_clr::P11_W
- gpio0::en2_clr::P12_W
- gpio0::en2_clr::P13_W
- gpio0::en2_clr::P1_W
- gpio0::en2_clr::P2_W
- gpio0::en2_clr::P3_W
- gpio0::en2_clr::P4_W
- gpio0::en2_clr::P5_W
- gpio0::en2_clr::P6_W
- gpio0::en2_clr::P7_W
- gpio0::en2_clr::P8_W
- gpio0::en2_clr::P9_W
- gpio0::en2_clr::W
- gpio0::en2_set::P0_W
- gpio0::en2_set::P10_W
- gpio0::en2_set::P11_W
- gpio0::en2_set::P12_W
- gpio0::en2_set::P13_W
- gpio0::en2_set::P1_W
- gpio0::en2_set::P2_W
- gpio0::en2_set::P3_W
- gpio0::en2_set::P4_W
- gpio0::en2_set::P5_W
- gpio0::en2_set::P6_W
- gpio0::en2_set::P7_W
- gpio0::en2_set::P8_W
- gpio0::en2_set::P9_W
- gpio0::en2_set::W
- gpio0::in_::P0_R
- gpio0::in_::P10_R
- gpio0::in_::P11_R
- gpio0::in_::P12_R
- gpio0::in_::P13_R
- gpio0::in_::P1_R
- gpio0::in_::P2_R
- gpio0::in_::P3_R
- gpio0::in_::P4_R
- gpio0::in_::P5_R
- gpio0::in_::P6_R
- gpio0::in_::P7_R
- gpio0::in_::P8_R
- gpio0::in_::P9_R
- gpio0::in_::R
- gpio0::int_clr::P0_W
- gpio0::int_clr::P10_W
- gpio0::int_clr::P11_W
- gpio0::int_clr::P12_W
- gpio0::int_clr::P13_W
- gpio0::int_clr::P1_W
- gpio0::int_clr::P2_W
- gpio0::int_clr::P3_W
- gpio0::int_clr::P4_W
- gpio0::int_clr::P5_W
- gpio0::int_clr::P6_W
- gpio0::int_clr::P7_W
- gpio0::int_clr::P8_W
- gpio0::int_clr::P9_W
- gpio0::int_clr::W
- gpio0::int_dual_edge::P0_R
- gpio0::int_dual_edge::P0_W
- gpio0::int_dual_edge::P10_R
- gpio0::int_dual_edge::P10_W
- gpio0::int_dual_edge::P11_R
- gpio0::int_dual_edge::P11_W
- gpio0::int_dual_edge::P12_R
- gpio0::int_dual_edge::P12_W
- gpio0::int_dual_edge::P13_R
- gpio0::int_dual_edge::P13_W
- gpio0::int_dual_edge::P1_R
- gpio0::int_dual_edge::P1_W
- gpio0::int_dual_edge::P2_R
- gpio0::int_dual_edge::P2_W
- gpio0::int_dual_edge::P3_R
- gpio0::int_dual_edge::P3_W
- gpio0::int_dual_edge::P4_R
- gpio0::int_dual_edge::P4_W
- gpio0::int_dual_edge::P5_R
- gpio0::int_dual_edge::P5_W
- gpio0::int_dual_edge::P6_R
- gpio0::int_dual_edge::P6_W
- gpio0::int_dual_edge::P7_R
- gpio0::int_dual_edge::P7_W
- gpio0::int_dual_edge::P8_R
- gpio0::int_dual_edge::P8_W
- gpio0::int_dual_edge::P9_R
- gpio0::int_dual_edge::P9_W
- gpio0::int_dual_edge::R
- gpio0::int_dual_edge::W
- gpio0::int_en::P0_R
- gpio0::int_en::P0_W
- gpio0::int_en::P10_R
- gpio0::int_en::P10_W
- gpio0::int_en::P11_R
- gpio0::int_en::P11_W
- gpio0::int_en::P12_R
- gpio0::int_en::P12_W
- gpio0::int_en::P13_R
- gpio0::int_en::P13_W
- gpio0::int_en::P1_R
- gpio0::int_en::P1_W
- gpio0::int_en::P2_R
- gpio0::int_en::P2_W
- gpio0::int_en::P3_R
- gpio0::int_en::P3_W
- gpio0::int_en::P4_R
- gpio0::int_en::P4_W
- gpio0::int_en::P5_R
- gpio0::int_en::P5_W
- gpio0::int_en::P6_R
- gpio0::int_en::P6_W
- gpio0::int_en::P7_R
- gpio0::int_en::P7_W
- gpio0::int_en::P8_R
- gpio0::int_en::P8_W
- gpio0::int_en::P9_R
- gpio0::int_en::P9_W
- gpio0::int_en::R
- gpio0::int_en::W
- gpio0::int_en_clr::P0_W
- gpio0::int_en_clr::P10_W
- gpio0::int_en_clr::P11_W
- gpio0::int_en_clr::P12_W
- gpio0::int_en_clr::P13_W
- gpio0::int_en_clr::P1_W
- gpio0::int_en_clr::P2_W
- gpio0::int_en_clr::P3_W
- gpio0::int_en_clr::P4_W
- gpio0::int_en_clr::P5_W
- gpio0::int_en_clr::P6_W
- gpio0::int_en_clr::P7_W
- gpio0::int_en_clr::P8_W
- gpio0::int_en_clr::P9_W
- gpio0::int_en_clr::W
- gpio0::int_en_set::P0_W
- gpio0::int_en_set::P10_W
- gpio0::int_en_set::P11_W
- gpio0::int_en_set::P12_W
- gpio0::int_en_set::P13_W
- gpio0::int_en_set::P1_W
- gpio0::int_en_set::P2_W
- gpio0::int_en_set::P3_W
- gpio0::int_en_set::P4_W
- gpio0::int_en_set::P5_W
- gpio0::int_en_set::P6_W
- gpio0::int_en_set::P7_W
- gpio0::int_en_set::P8_W
- gpio0::int_en_set::P9_W
- gpio0::int_en_set::W
- gpio0::int_mode::P0_R
- gpio0::int_mode::P0_W
- gpio0::int_mode::P10_R
- gpio0::int_mode::P10_W
- gpio0::int_mode::P11_R
- gpio0::int_mode::P11_W
- gpio0::int_mode::P12_R
- gpio0::int_mode::P12_W
- gpio0::int_mode::P13_R
- gpio0::int_mode::P13_W
- gpio0::int_mode::P1_R
- gpio0::int_mode::P1_W
- gpio0::int_mode::P2_R
- gpio0::int_mode::P2_W
- gpio0::int_mode::P3_R
- gpio0::int_mode::P3_W
- gpio0::int_mode::P4_R
- gpio0::int_mode::P4_W
- gpio0::int_mode::P5_R
- gpio0::int_mode::P5_W
- gpio0::int_mode::P6_R
- gpio0::int_mode::P6_W
- gpio0::int_mode::P7_R
- gpio0::int_mode::P7_W
- gpio0::int_mode::P8_R
- gpio0::int_mode::P8_W
- gpio0::int_mode::P9_R
- gpio0::int_mode::P9_W
- gpio0::int_mode::R
- gpio0::int_mode::W
- gpio0::int_pol::P0_R
- gpio0::int_pol::P0_W
- gpio0::int_pol::P10_R
- gpio0::int_pol::P10_W
- gpio0::int_pol::P11_R
- gpio0::int_pol::P11_W
- gpio0::int_pol::P12_R
- gpio0::int_pol::P12_W
- gpio0::int_pol::P13_R
- gpio0::int_pol::P13_W
- gpio0::int_pol::P1_R
- gpio0::int_pol::P1_W
- gpio0::int_pol::P2_R
- gpio0::int_pol::P2_W
- gpio0::int_pol::P3_R
- gpio0::int_pol::P3_W
- gpio0::int_pol::P4_R
- gpio0::int_pol::P4_W
- gpio0::int_pol::P5_R
- gpio0::int_pol::P5_W
- gpio0::int_pol::P6_R
- gpio0::int_pol::P6_W
- gpio0::int_pol::P7_R
- gpio0::int_pol::P7_W
- gpio0::int_pol::P8_R
- gpio0::int_pol::P8_W
- gpio0::int_pol::P9_R
- gpio0::int_pol::P9_W
- gpio0::int_pol::R
- gpio0::int_pol::W
- gpio0::int_stat::P0_R
- gpio0::int_stat::P10_R
- gpio0::int_stat::P11_R
- gpio0::int_stat::P12_R
- gpio0::int_stat::P13_R
- gpio0::int_stat::P1_R
- gpio0::int_stat::P2_R
- gpio0::int_stat::P3_R
- gpio0::int_stat::P4_R
- gpio0::int_stat::P5_R
- gpio0::int_stat::P6_R
- gpio0::int_stat::P7_R
- gpio0::int_stat::P8_R
- gpio0::int_stat::P9_R
- gpio0::int_stat::R
- gpio0::is::P0_R
- gpio0::is::P0_W
- gpio0::is::P10_R
- gpio0::is::P10_W
- gpio0::is::P11_R
- gpio0::is::P11_W
- gpio0::is::P12_R
- gpio0::is::P12_W
- gpio0::is::P13_R
- gpio0::is::P13_W
- gpio0::is::P1_R
- gpio0::is::P1_W
- gpio0::is::P2_R
- gpio0::is::P2_W
- gpio0::is::P3_R
- gpio0::is::P3_W
- gpio0::is::P4_R
- gpio0::is::P4_W
- gpio0::is::P5_R
- gpio0::is::P5_W
- gpio0::is::P6_R
- gpio0::is::P6_W
- gpio0::is::P7_R
- gpio0::is::P7_W
- gpio0::is::P8_R
- gpio0::is::P8_W
- gpio0::is::P9_R
- gpio0::is::P9_W
- gpio0::is::R
- gpio0::is::W
- gpio0::out::P0_R
- gpio0::out::P0_W
- gpio0::out::P10_R
- gpio0::out::P10_W
- gpio0::out::P11_R
- gpio0::out::P11_W
- gpio0::out::P12_R
- gpio0::out::P12_W
- gpio0::out::P13_R
- gpio0::out::P13_W
- gpio0::out::P1_R
- gpio0::out::P1_W
- gpio0::out::P2_R
- gpio0::out::P2_W
- gpio0::out::P3_R
- gpio0::out::P3_W
- gpio0::out::P4_R
- gpio0::out::P4_W
- gpio0::out::P5_R
- gpio0::out::P5_W
- gpio0::out::P6_R
- gpio0::out::P6_W
- gpio0::out::P7_R
- gpio0::out::P7_W
- gpio0::out::P8_R
- gpio0::out::P8_W
- gpio0::out::P9_R
- gpio0::out::P9_W
- gpio0::out::R
- gpio0::out::W
- gpio0::out_clr::P0_W
- gpio0::out_clr::P10_W
- gpio0::out_clr::P11_W
- gpio0::out_clr::P12_W
- gpio0::out_clr::P13_W
- gpio0::out_clr::P1_W
- gpio0::out_clr::P2_W
- gpio0::out_clr::P3_W
- gpio0::out_clr::P4_W
- gpio0::out_clr::P5_W
- gpio0::out_clr::P6_W
- gpio0::out_clr::P7_W
- gpio0::out_clr::P8_W
- gpio0::out_clr::P9_W
- gpio0::out_clr::W
- gpio0::out_en::P0_R
- gpio0::out_en::P0_W
- gpio0::out_en::P10_R
- gpio0::out_en::P10_W
- gpio0::out_en::P11_R
- gpio0::out_en::P11_W
- gpio0::out_en::P12_R
- gpio0::out_en::P12_W
- gpio0::out_en::P13_R
- gpio0::out_en::P13_W
- gpio0::out_en::P1_R
- gpio0::out_en::P1_W
- gpio0::out_en::P2_R
- gpio0::out_en::P2_W
- gpio0::out_en::P3_R
- gpio0::out_en::P3_W
- gpio0::out_en::P4_R
- gpio0::out_en::P4_W
- gpio0::out_en::P5_R
- gpio0::out_en::P5_W
- gpio0::out_en::P6_R
- gpio0::out_en::P6_W
- gpio0::out_en::P7_R
- gpio0::out_en::P7_W
- gpio0::out_en::P8_R
- gpio0::out_en::P8_W
- gpio0::out_en::P9_R
- gpio0::out_en::P9_W
- gpio0::out_en::R
- gpio0::out_en::W
- gpio0::out_en_clr::P0_W
- gpio0::out_en_clr::P10_W
- gpio0::out_en_clr::P11_W
- gpio0::out_en_clr::P12_W
- gpio0::out_en_clr::P13_W
- gpio0::out_en_clr::P1_W
- gpio0::out_en_clr::P2_W
- gpio0::out_en_clr::P3_W
- gpio0::out_en_clr::P4_W
- gpio0::out_en_clr::P5_W
- gpio0::out_en_clr::P6_W
- gpio0::out_en_clr::P7_W
- gpio0::out_en_clr::P8_W
- gpio0::out_en_clr::P9_W
- gpio0::out_en_clr::W
- gpio0::out_en_set::P0_W
- gpio0::out_en_set::P10_W
- gpio0::out_en_set::P11_W
- gpio0::out_en_set::P12_W
- gpio0::out_en_set::P13_W
- gpio0::out_en_set::P1_W
- gpio0::out_en_set::P2_W
- gpio0::out_en_set::P3_W
- gpio0::out_en_set::P4_W
- gpio0::out_en_set::P5_W
- gpio0::out_en_set::P6_W
- gpio0::out_en_set::P7_W
- gpio0::out_en_set::P8_W
- gpio0::out_en_set::P9_W
- gpio0::out_en_set::W
- gpio0::out_set::P0_W
- gpio0::out_set::P10_W
- gpio0::out_set::P11_W
- gpio0::out_set::P12_W
- gpio0::out_set::P13_W
- gpio0::out_set::P1_W
- gpio0::out_set::P2_W
- gpio0::out_set::P3_W
- gpio0::out_set::P4_W
- gpio0::out_set::P5_W
- gpio0::out_set::P6_W
- gpio0::out_set::P7_W
- gpio0::out_set::P8_W
- gpio0::out_set::P9_W
- gpio0::out_set::W
- gpio0::pad_cfg::P0_R
- gpio0::pad_cfg::P0_W
- gpio0::pad_cfg::P10_R
- gpio0::pad_cfg::P10_W
- gpio0::pad_cfg::P11_R
- gpio0::pad_cfg::P11_W
- gpio0::pad_cfg::P12_R
- gpio0::pad_cfg::P12_W
- gpio0::pad_cfg::P13_R
- gpio0::pad_cfg::P13_W
- gpio0::pad_cfg::P1_R
- gpio0::pad_cfg::P1_W
- gpio0::pad_cfg::P2_R
- gpio0::pad_cfg::P2_W
- gpio0::pad_cfg::P3_R
- gpio0::pad_cfg::P3_W
- gpio0::pad_cfg::P4_R
- gpio0::pad_cfg::P4_W
- gpio0::pad_cfg::P5_R
- gpio0::pad_cfg::P5_W
- gpio0::pad_cfg::P6_R
- gpio0::pad_cfg::P6_W
- gpio0::pad_cfg::P7_R
- gpio0::pad_cfg::P7_W
- gpio0::pad_cfg::P8_R
- gpio0::pad_cfg::P8_W
- gpio0::pad_cfg::P9_R
- gpio0::pad_cfg::P9_W
- gpio0::pad_cfg::R
- gpio0::pad_cfg::W
- gpio0::ps::P0_R
- gpio0::ps::P0_W
- gpio0::ps::P10_R
- gpio0::ps::P10_W
- gpio0::ps::P11_R
- gpio0::ps::P11_W
- gpio0::ps::P12_R
- gpio0::ps::P12_W
- gpio0::ps::P13_R
- gpio0::ps::P13_W
- gpio0::ps::P1_R
- gpio0::ps::P1_W
- gpio0::ps::P2_R
- gpio0::ps::P2_W
- gpio0::ps::P3_R
- gpio0::ps::P3_W
- gpio0::ps::P4_R
- gpio0::ps::P4_W
- gpio0::ps::P5_R
- gpio0::ps::P5_W
- gpio0::ps::P6_R
- gpio0::ps::P6_W
- gpio0::ps::P7_R
- gpio0::ps::P7_W
- gpio0::ps::P8_R
- gpio0::ps::P8_W
- gpio0::ps::P9_R
- gpio0::ps::P9_W
- gpio0::ps::R
- gpio0::ps::W
- gpio0::sr::P0_R
- gpio0::sr::P0_W
- gpio0::sr::P10_R
- gpio0::sr::P10_W
- gpio0::sr::P11_R
- gpio0::sr::P11_W
- gpio0::sr::P12_R
- gpio0::sr::P12_W
- gpio0::sr::P13_R
- gpio0::sr::P13_W
- gpio0::sr::P1_R
- gpio0::sr::P1_W
- gpio0::sr::P2_R
- gpio0::sr::P2_W
- gpio0::sr::P3_R
- gpio0::sr::P3_W
- gpio0::sr::P4_R
- gpio0::sr::P4_W
- gpio0::sr::P5_R
- gpio0::sr::P5_W
- gpio0::sr::P6_R
- gpio0::sr::P6_W
- gpio0::sr::P7_R
- gpio0::sr::P7_W
- gpio0::sr::P8_R
- gpio0::sr::P8_W
- gpio0::sr::P9_R
- gpio0::sr::P9_W
- gpio0::sr::R
- gpio0::sr::W
- gpio0::wake_en::P0_R
- gpio0::wake_en::P0_W
- gpio0::wake_en::P10_R
- gpio0::wake_en::P10_W
- gpio0::wake_en::P11_R
- gpio0::wake_en::P11_W
- gpio0::wake_en::P12_R
- gpio0::wake_en::P12_W
- gpio0::wake_en::P13_R
- gpio0::wake_en::P13_W
- gpio0::wake_en::P1_R
- gpio0::wake_en::P1_W
- gpio0::wake_en::P2_R
- gpio0::wake_en::P2_W
- gpio0::wake_en::P3_R
- gpio0::wake_en::P3_W
- gpio0::wake_en::P4_R
- gpio0::wake_en::P4_W
- gpio0::wake_en::P5_R
- gpio0::wake_en::P5_W
- gpio0::wake_en::P6_R
- gpio0::wake_en::P6_W
- gpio0::wake_en::P7_R
- gpio0::wake_en::P7_W
- gpio0::wake_en::P8_R
- gpio0::wake_en::P8_W
- gpio0::wake_en::P9_R
- gpio0::wake_en::P9_W
- gpio0::wake_en::R
- gpio0::wake_en::W
- gpio0::wake_en_clr::P0_W
- gpio0::wake_en_clr::P10_W
- gpio0::wake_en_clr::P11_W
- gpio0::wake_en_clr::P12_W
- gpio0::wake_en_clr::P13_W
- gpio0::wake_en_clr::P1_W
- gpio0::wake_en_clr::P2_W
- gpio0::wake_en_clr::P3_W
- gpio0::wake_en_clr::P4_W
- gpio0::wake_en_clr::P5_W
- gpio0::wake_en_clr::P6_W
- gpio0::wake_en_clr::P7_W
- gpio0::wake_en_clr::P8_W
- gpio0::wake_en_clr::P9_W
- gpio0::wake_en_clr::W
- gpio0::wake_en_set::P0_W
- gpio0::wake_en_set::P10_W
- gpio0::wake_en_set::P11_W
- gpio0::wake_en_set::P12_W
- gpio0::wake_en_set::P13_W
- gpio0::wake_en_set::P1_W
- gpio0::wake_en_set::P2_W
- gpio0::wake_en_set::P3_W
- gpio0::wake_en_set::P4_W
- gpio0::wake_en_set::P5_W
- gpio0::wake_en_set::P6_W
- gpio0::wake_en_set::P7_W
- gpio0::wake_en_set::P8_W
- gpio0::wake_en_set::P9_W
- gpio0::wake_en_set::W
- i2c0::CLKHI
- i2c0::CLKLO
- i2c0::CTRL0
- i2c0::DMA
- i2c0::FIFO
- i2c0::FIFOLEN
- i2c0::HS_CLK
- i2c0::INTEN0
- i2c0::INTEN1
- i2c0::INTFL0
- i2c0::INTFL1
- i2c0::MSTR_MODE
- i2c0::RXCTRL0
- i2c0::RXCTRL1
- i2c0::SLADDR
- i2c0::STATUS
- i2c0::TIMEOUT
- i2c0::TXCTRL0
- i2c0::TXCTRL1
- i2c0::clkhi::R
- i2c0::clkhi::SCL_HI_R
- i2c0::clkhi::SCL_HI_W
- i2c0::clkhi::W
- i2c0::clklo::R
- i2c0::clklo::SCL_LO_R
- i2c0::clklo::SCL_LO_W
- i2c0::clklo::W
- i2c0::ctrl0::ACK_R
- i2c0::ctrl0::ACK_W
- i2c0::ctrl0::GCEN_R
- i2c0::ctrl0::GCEN_W
- i2c0::ctrl0::HSMODE_R
- i2c0::ctrl0::HSMODE_W
- i2c0::ctrl0::I2CEN_R
- i2c0::ctrl0::I2CEN_W
- i2c0::ctrl0::IRXM_R
- i2c0::ctrl0::IRXM_W
- i2c0::ctrl0::MST_R
- i2c0::ctrl0::MST_W
- i2c0::ctrl0::R
- i2c0::ctrl0::READ_R
- i2c0::ctrl0::SCLO_R
- i2c0::ctrl0::SCLO_W
- i2c0::ctrl0::SCL_PPM_R
- i2c0::ctrl0::SCL_PPM_W
- i2c0::ctrl0::SCL_R
- i2c0::ctrl0::SCL_STRD_R
- i2c0::ctrl0::SCL_STRD_W
- i2c0::ctrl0::SDAO_R
- i2c0::ctrl0::SDAO_W
- i2c0::ctrl0::SDA_R
- i2c0::ctrl0::SWOE_R
- i2c0::ctrl0::SWOE_W
- i2c0::ctrl0::W
- i2c0::dma::R
- i2c0::dma::RXEN_R
- i2c0::dma::RXEN_W
- i2c0::dma::TXEN_R
- i2c0::dma::TXEN_W
- i2c0::dma::W
- i2c0::fifo::DATA_R
- i2c0::fifo::DATA_W
- i2c0::fifo::R
- i2c0::fifo::W
- i2c0::fifolen::R
- i2c0::fifolen::RXLEN_R
- i2c0::fifolen::TXLEN_R
- i2c0::fifolen::W
- i2c0::hs_clk::HS_CLK_HI_R
- i2c0::hs_clk::HS_CLK_HI_W
- i2c0::hs_clk::HS_CLK_LO_R
- i2c0::hs_clk::HS_CLK_LO_W
- i2c0::hs_clk::R
- i2c0::hs_clk::W
- i2c0::inten0::ADRACKIE_R
- i2c0::inten0::ADRACKIE_W
- i2c0::inten0::ADRERIE_R
- i2c0::inten0::ADRERIE_W
- i2c0::inten0::AMIE_R
- i2c0::inten0::AMIE_W
- i2c0::inten0::ARBERIE_R
- i2c0::inten0::ARBERIE_W
- i2c0::inten0::DATERIE_R
- i2c0::inten0::DATERIE_W
- i2c0::inten0::DNRERIE_R
- i2c0::inten0::DNRERIE_W
- i2c0::inten0::DONEIE_R
- i2c0::inten0::DONEIE_W
- i2c0::inten0::GCIE_R
- i2c0::inten0::GCIE_W
- i2c0::inten0::IRXMIE_R
- i2c0::inten0::IRXMIE_W
- i2c0::inten0::MAMIE_R
- i2c0::inten0::MAMIE_W
- i2c0::inten0::R
- i2c0::inten0::RXTHIE_R
- i2c0::inten0::RXTHIE_W
- i2c0::inten0::STOPERIE_R
- i2c0::inten0::STOPERIE_W
- i2c0::inten0::STOPIE_R
- i2c0::inten0::STOPIE_W
- i2c0::inten0::STRTERIE_R
- i2c0::inten0::STRTERIE_W
- i2c0::inten0::TOERIE_R
- i2c0::inten0::TOERIE_W
- i2c0::inten0::TXLOIE_R
- i2c0::inten0::TXLOIE_W
- i2c0::inten0::TXTHIE_R
- i2c0::inten0::TXTHIE_W
- i2c0::inten0::W
- i2c0::inten1::R
- i2c0::inten1::RXOFIE_R
- i2c0::inten1::RXOFIE_W
- i2c0::inten1::TXUFIE_R
- i2c0::inten1::TXUFIE_W
- i2c0::inten1::W
- i2c0::intfl0::ADRACKI_R
- i2c0::intfl0::ADRACKI_W
- i2c0::intfl0::ADRERI_R
- i2c0::intfl0::ADRERI_W
- i2c0::intfl0::AMI_R
- i2c0::intfl0::AMI_W
- i2c0::intfl0::ARBERI_R
- i2c0::intfl0::ARBERI_W
- i2c0::intfl0::DATERI_R
- i2c0::intfl0::DATERI_W
- i2c0::intfl0::DNRERI_R
- i2c0::intfl0::DNRERI_W
- i2c0::intfl0::DONEI_R
- i2c0::intfl0::DONEI_W
- i2c0::intfl0::GCI_R
- i2c0::intfl0::GCI_W
- i2c0::intfl0::IRXMI_R
- i2c0::intfl0::IRXMI_W
- i2c0::intfl0::MAMI_R
- i2c0::intfl0::MAMI_W
- i2c0::intfl0::R
- i2c0::intfl0::RXTHI_R
- i2c0::intfl0::RXTHI_W
- i2c0::intfl0::STOPERI_R
- i2c0::intfl0::STOPERI_W
- i2c0::intfl0::STOPI_R
- i2c0::intfl0::STOPI_W
- i2c0::intfl0::STRTERI_R
- i2c0::intfl0::STRTERI_W
- i2c0::intfl0::TOERI_R
- i2c0::intfl0::TOERI_W
- i2c0::intfl0::TXLOI_R
- i2c0::intfl0::TXLOI_W
- i2c0::intfl0::TXTHI_R
- i2c0::intfl0::TXTHI_W
- i2c0::intfl0::W
- i2c0::intfl1::R
- i2c0::intfl1::RXOFI_R
- i2c0::intfl1::RXOFI_W
- i2c0::intfl1::TXUFI_R
- i2c0::intfl1::TXUFI_W
- i2c0::intfl1::W
- i2c0::mstr_mode::R
- i2c0::mstr_mode::RESTART_R
- i2c0::mstr_mode::RESTART_W
- i2c0::mstr_mode::SEA_R
- i2c0::mstr_mode::SEA_W
- i2c0::mstr_mode::START_R
- i2c0::mstr_mode::START_W
- i2c0::mstr_mode::STOP_R
- i2c0::mstr_mode::STOP_W
- i2c0::mstr_mode::W
- i2c0::rxctrl0::DNR_R
- i2c0::rxctrl0::DNR_W
- i2c0::rxctrl0::R
- i2c0::rxctrl0::RXFSH_R
- i2c0::rxctrl0::RXFSH_W
- i2c0::rxctrl0::RXTH_R
- i2c0::rxctrl0::RXTH_W
- i2c0::rxctrl0::W
- i2c0::rxctrl1::R
- i2c0::rxctrl1::RXCNT_R
- i2c0::rxctrl1::RXCNT_W
- i2c0::rxctrl1::RXFIFO_R
- i2c0::rxctrl1::W
- i2c0::sladdr::EA_R
- i2c0::sladdr::EA_W
- i2c0::sladdr::R
- i2c0::sladdr::SLADIS_R
- i2c0::sladdr::SLADIS_W
- i2c0::sladdr::SLAIDX_R
- i2c0::sladdr::SLAIDX_W
- i2c0::sladdr::SLA_R
- i2c0::sladdr::SLA_W
- i2c0::sladdr::W
- i2c0::status::BUSY_R
- i2c0::status::CKMD_R
- i2c0::status::R
- i2c0::status::RXE_R
- i2c0::status::RXF_R
- i2c0::status::STAT_R
- i2c0::status::STAT_W
- i2c0::status::TXE_R
- i2c0::status::TXE_W
- i2c0::status::TXF_R
- i2c0::status::TXF_W
- i2c0::status::W
- i2c0::timeout::R
- i2c0::timeout::TO_R
- i2c0::timeout::TO_W
- i2c0::timeout::W
- i2c0::txctrl0::R
- i2c0::txctrl0::TXFSH_R
- i2c0::txctrl0::TXFSH_W
- i2c0::txctrl0::TXPRELD_R
- i2c0::txctrl0::TXPRELD_W
- i2c0::txctrl0::TXTH_R
- i2c0::txctrl0::TXTH_W
- i2c0::txctrl0::TX_READY_MODE_R
- i2c0::txctrl0::TX_READY_MODE_W
- i2c0::txctrl0::W
- i2c0::txctrl1::FLSH_GCADDR_DIS_R
- i2c0::txctrl1::FLSH_GCADDR_DIS_W
- i2c0::txctrl1::FLSH_NACK_DIS_R
- i2c0::txctrl1::FLSH_NACK_DIS_W
- i2c0::txctrl1::FLSH_SLADDR_DIS_R
- i2c0::txctrl1::FLSH_SLADDR_DIS_W
- i2c0::txctrl1::R
- i2c0::txctrl1::TXFIFO_R
- i2c0::txctrl1::TXLAST_R
- i2c0::txctrl1::TXLAST_W
- i2c0::txctrl1::TXRDY_R
- i2c0::txctrl1::TXRDY_W
- i2c0::txctrl1::W
- icc::CACHE_CTRL
- icc::CACHE_ID
- icc::INVALIDATE
- icc::MEM_SIZE
- icc::cache_ctrl::ENABLED_R
- icc::cache_ctrl::ENABLED_W
- icc::cache_ctrl::R
- icc::cache_ctrl::READY_R
- icc::cache_ctrl::W
- icc::cache_id::CCHID_R
- icc::cache_id::PARTNUM_R
- icc::cache_id::R
- icc::cache_id::RELNUM_R
- icc::invalidate::R
- icc::invalidate::W
- icc::mem_size::CCHSZ_R
- icc::mem_size::MEMSZ_R
- icc::mem_size::R
- pwrseq::LPMEMSD
- pwrseq::LPWK_EN
- pwrseq::LP_CTRL
- pwrseq::LP_WAKEFL
- pwrseq::lp_ctrl::BG_OFF_R
- pwrseq::lp_ctrl::BG_OFF_W
- pwrseq::lp_ctrl::FAST_WK_EN_R
- pwrseq::lp_ctrl::FAST_WK_EN_W
- pwrseq::lp_ctrl::LDO_DIS_R
- pwrseq::lp_ctrl::LDO_DIS_W
- pwrseq::lp_ctrl::OVR_R
- pwrseq::lp_ctrl::OVR_W
- pwrseq::lp_ctrl::R
- pwrseq::lp_ctrl::RAMRET_SEL0_R
- pwrseq::lp_ctrl::RAMRET_SEL0_W
- pwrseq::lp_ctrl::RAMRET_SEL1_R
- pwrseq::lp_ctrl::RAMRET_SEL1_W
- pwrseq::lp_ctrl::RAMRET_SEL2_R
- pwrseq::lp_ctrl::RAMRET_SEL2_W
- pwrseq::lp_ctrl::RAMRET_SEL3_R
- pwrseq::lp_ctrl::RAMRET_SEL3_W
- pwrseq::lp_ctrl::RETREG_EN_R
- pwrseq::lp_ctrl::RETREG_EN_W
- pwrseq::lp_ctrl::VCORE_DET_BYPASS_R
- pwrseq::lp_ctrl::VCORE_DET_BYPASS_W
- pwrseq::lp_ctrl::VCORE_POR_DIS_R
- pwrseq::lp_ctrl::VCORE_POR_DIS_W
- pwrseq::lp_ctrl::VCORE_SVM_DIS_R
- pwrseq::lp_ctrl::VCORE_SVM_DIS_W
- pwrseq::lp_ctrl::VDDIO_POR_DIS_R
- pwrseq::lp_ctrl::VDDIO_POR_DIS_W
- pwrseq::lp_ctrl::W
- pwrseq::lp_wakefl::R
- pwrseq::lp_wakefl::W
- pwrseq::lp_wakefl::WAKEST_R
- pwrseq::lp_wakefl::WAKEST_W
- pwrseq::lpmemsd::R
- pwrseq::lpmemsd::SRAM0_OFF_R
- pwrseq::lpmemsd::SRAM0_OFF_W
- pwrseq::lpmemsd::SRAM1_OFF_R
- pwrseq::lpmemsd::SRAM1_OFF_W
- pwrseq::lpmemsd::SRAM2_OFF_R
- pwrseq::lpmemsd::SRAM2_OFF_W
- pwrseq::lpmemsd::SRAM3_OFF_R
- pwrseq::lpmemsd::SRAM3_OFF_W
- pwrseq::lpmemsd::W
- pwrseq::lpwk_en::R
- pwrseq::lpwk_en::W
- pwrseq::lpwk_en::WAKEEN_R
- pwrseq::lpwk_en::WAKEEN_W
- rtc::CTRL
- rtc::OSCCTRL
- rtc::RAS
- rtc::RSSA
- rtc::SEC
- rtc::SSEC
- rtc::TRIM
- rtc::ctrl::ADE_R
- rtc::ctrl::ADE_W
- rtc::ctrl::ALDF_R
- rtc::ctrl::ALDF_W
- rtc::ctrl::ALSF_R
- rtc::ctrl::ALSF_W
- rtc::ctrl::ASE_R
- rtc::ctrl::ASE_W
- rtc::ctrl::BUSY_R
- rtc::ctrl::FT_R
- rtc::ctrl::FT_W
- rtc::ctrl::R
- rtc::ctrl::RDYE_R
- rtc::ctrl::RDYE_W
- rtc::ctrl::RDY_R
- rtc::ctrl::RDY_W
- rtc::ctrl::RTCE_R
- rtc::ctrl::RTCE_W
- rtc::ctrl::SQE_R
- rtc::ctrl::SQE_W
- rtc::ctrl::W
- rtc::ctrl::WE_R
- rtc::ctrl::WE_W
- rtc::ctrl::X32KMD_R
- rtc::ctrl::X32KMD_W
- rtc::oscctrl::BYPASS_R
- rtc::oscctrl::BYPASS_W
- rtc::oscctrl::FILTER_EN_R
- rtc::oscctrl::FILTER_EN_W
- rtc::oscctrl::HYST_EN_R
- rtc::oscctrl::HYST_EN_W
- rtc::oscctrl::IBIAS_EN_R
- rtc::oscctrl::IBIAS_EN_W
- rtc::oscctrl::IBIAS_SEL_R
- rtc::oscctrl::IBIAS_SEL_W
- rtc::oscctrl::OUT32K_R
- rtc::oscctrl::OUT32K_W
- rtc::oscctrl::R
- rtc::oscctrl::W
- rtc::ras::R
- rtc::ras::RAS_R
- rtc::ras::RAS_W
- rtc::ras::W
- rtc::rssa::R
- rtc::rssa::RSSA_R
- rtc::rssa::RSSA_W
- rtc::rssa::W
- rtc::sec::R
- rtc::sec::W
- rtc::ssec::R
- rtc::ssec::RTSS_R
- rtc::ssec::RTSS_W
- rtc::ssec::W
- rtc::trim::R
- rtc::trim::TRIM_R
- rtc::trim::TRIM_W
- rtc::trim::VBATTMR_R
- rtc::trim::VBATTMR_W
- rtc::trim::W
- sir::ADDR
- sir::STATUS
- sir::addr::ADDR_R
- sir::addr::R
- sir::status::CFG_ERR_R
- sir::status::CFG_VALID_R
- sir::status::R
- spi0::CLK_CFG
- spi0::CTRL0
- spi0::CTRL1
- spi0::CTRL2
- spi0::DATA
- spi0::DMA
- spi0::INT_EN
- spi0::INT_FL
- spi0::SS_TIME
- spi0::STAT
- spi0::WAKE_EN
- spi0::WAKE_FL
- spi0::clk_cfg::HI_R
- spi0::clk_cfg::HI_W
- spi0::clk_cfg::LO_R
- spi0::clk_cfg::LO_W
- spi0::clk_cfg::R
- spi0::clk_cfg::SCALE_R
- spi0::clk_cfg::SCALE_W
- spi0::clk_cfg::W
- spi0::ctrl0::MM_EN_R
- spi0::ctrl0::MM_EN_W
- spi0::ctrl0::R
- spi0::ctrl0::SPI_EN_R
- spi0::ctrl0::SPI_EN_W
- spi0::ctrl0::SS_CTRL_R
- spi0::ctrl0::SS_CTRL_W
- spi0::ctrl0::SS_IO_R
- spi0::ctrl0::SS_IO_W
- spi0::ctrl0::SS_SEL_R
- spi0::ctrl0::SS_SEL_W
- spi0::ctrl0::START_R
- spi0::ctrl0::START_W
- spi0::ctrl0::W
- spi0::ctrl1::R
- spi0::ctrl1::RX_NUM_CHAR_R
- spi0::ctrl1::RX_NUM_CHAR_W
- spi0::ctrl1::TX_NUM_CHAR_R
- spi0::ctrl1::TX_NUM_CHAR_W
- spi0::ctrl1::W
- spi0::ctrl2::CLK_PHA_R
- spi0::ctrl2::CLK_PHA_W
- spi0::ctrl2::CLK_POL_R
- spi0::ctrl2::CLK_POL_W
- spi0::ctrl2::DATA_WIDTH_R
- spi0::ctrl2::DATA_WIDTH_W
- spi0::ctrl2::NUM_BITS_R
- spi0::ctrl2::NUM_BITS_W
- spi0::ctrl2::R
- spi0::ctrl2::SS_POL_R
- spi0::ctrl2::SS_POL_W
- spi0::ctrl2::THREE_WIRE_R
- spi0::ctrl2::THREE_WIRE_W
- spi0::ctrl2::W
- spi0::data::DATA_R
- spi0::data::DATA_W
- spi0::data::R
- spi0::data::W
- spi0::dma::R
- spi0::dma::RX_DMA_EN_R
- spi0::dma::RX_DMA_EN_W
- spi0::dma::RX_FIFO_CLEAR_R
- spi0::dma::RX_FIFO_CLEAR_W
- spi0::dma::RX_FIFO_CNT_R
- spi0::dma::RX_FIFO_EN_R
- spi0::dma::RX_FIFO_EN_W
- spi0::dma::RX_FIFO_LEVEL_R
- spi0::dma::RX_FIFO_LEVEL_W
- spi0::dma::TX_DMA_EN_R
- spi0::dma::TX_DMA_EN_W
- spi0::dma::TX_FIFO_CLEAR_R
- spi0::dma::TX_FIFO_CLEAR_W
- spi0::dma::TX_FIFO_CNT_R
- spi0::dma::TX_FIFO_EN_R
- spi0::dma::TX_FIFO_EN_W
- spi0::dma::TX_FIFO_LEVEL_R
- spi0::dma::TX_FIFO_LEVEL_W
- spi0::dma::W
- spi0::int_en::ABORT_R
- spi0::int_en::ABORT_W
- spi0::int_en::FAULT_R
- spi0::int_en::FAULT_W
- spi0::int_en::M_DONE_R
- spi0::int_en::M_DONE_W
- spi0::int_en::R
- spi0::int_en::RX_FULL_R
- spi0::int_en::RX_FULL_W
- spi0::int_en::RX_LEVEL_R
- spi0::int_en::RX_LEVEL_W
- spi0::int_en::RX_OVR_R
- spi0::int_en::RX_OVR_W
- spi0::int_en::RX_UND_R
- spi0::int_en::RX_UND_W
- spi0::int_en::SSA_R
- spi0::int_en::SSA_W
- spi0::int_en::SSD_R
- spi0::int_en::SSD_W
- spi0::int_en::TX_EMPTY_R
- spi0::int_en::TX_EMPTY_W
- spi0::int_en::TX_LEVEL_R
- spi0::int_en::TX_LEVEL_W
- spi0::int_en::TX_OVR_R
- spi0::int_en::TX_OVR_W
- spi0::int_en::TX_UND_R
- spi0::int_en::TX_UND_W
- spi0::int_en::W
- spi0::int_fl::ABORT_R
- spi0::int_fl::ABORT_W
- spi0::int_fl::M_DONE_R
- spi0::int_fl::M_DONE_W
- spi0::int_fl::R
- spi0::int_fl::RX_FULL_R
- spi0::int_fl::RX_FULL_W
- spi0::int_fl::RX_LEVEL_R
- spi0::int_fl::RX_LEVEL_W
- spi0::int_fl::RX_OVR_R
- spi0::int_fl::RX_OVR_W
- spi0::int_fl::RX_UND_R
- spi0::int_fl::RX_UND_W
- spi0::int_fl::SSA_R
- spi0::int_fl::SSA_W
- spi0::int_fl::SSD_R
- spi0::int_fl::SSD_W
- spi0::int_fl::TX_EMPTY_R
- spi0::int_fl::TX_EMPTY_W
- spi0::int_fl::TX_LEVEL_R
- spi0::int_fl::TX_LEVEL_W
- spi0::int_fl::TX_OVR_R
- spi0::int_fl::TX_OVR_W
- spi0::int_fl::TX_UND_R
- spi0::int_fl::TX_UND_W
- spi0::int_fl::W
- spi0::ss_time::R
- spi0::ss_time::SSACT1_R
- spi0::ss_time::SSACT1_W
- spi0::ss_time::SSACT2_R
- spi0::ss_time::SSACT2_W
- spi0::ss_time::SSINACT_R
- spi0::ss_time::SSINACT_W
- spi0::ss_time::W
- spi0::stat::BUSY_R
- spi0::stat::R
- spi0::wake_en::R
- spi0::wake_en::RX_FULL_R
- spi0::wake_en::RX_FULL_W
- spi0::wake_en::RX_LEVEL_R
- spi0::wake_en::RX_LEVEL_W
- spi0::wake_en::TX_EMPTY_R
- spi0::wake_en::TX_EMPTY_W
- spi0::wake_en::TX_LEVEL_R
- spi0::wake_en::TX_LEVEL_W
- spi0::wake_en::W
- spi0::wake_fl::R
- spi0::wake_fl::RX_FULL_R
- spi0::wake_fl::RX_FULL_W
- spi0::wake_fl::RX_LEVEL_R
- spi0::wake_fl::RX_LEVEL_W
- spi0::wake_fl::TX_EMPTY_R
- spi0::wake_fl::TX_EMPTY_W
- spi0::wake_fl::TX_LEVEL_R
- spi0::wake_fl::TX_LEVEL_W
- spi0::wake_fl::W
- spi1::BRG
- spi1::CTRL
- spi1::DATA
- spi1::DMA
- spi1::I2S_CTRL
- spi1::INT_FL
- spi1::MODE
- spi1::brg::DIV_R
- spi1::brg::DIV_W
- spi1::brg::R
- spi1::brg::W
- spi1::ctrl::BIRQ_R
- spi1::ctrl::BIRQ_W
- spi1::ctrl::CLKPOL_R
- spi1::ctrl::CLKPOL_W
- spi1::ctrl::ENABLED_R
- spi1::ctrl::ENABLED_W
- spi1::ctrl::IRQE_R
- spi1::ctrl::IRQE_W
- spi1::ctrl::MMEN_R
- spi1::ctrl::MMEN_W
- spi1::ctrl::PHASE_R
- spi1::ctrl::PHASE_W
- spi1::ctrl::R
- spi1::ctrl::STR_R
- spi1::ctrl::STR_W
- spi1::ctrl::W
- spi1::ctrl::WOR_R
- spi1::ctrl::WOR_W
- spi1::data::DATA_R
- spi1::data::DATA_W
- spi1::data::R
- spi1::data::W
- spi1::dma::R
- spi1::dma::RX_DMA_EN_R
- spi1::dma::RX_DMA_EN_W
- spi1::dma::RX_FIFO_CLR_R
- spi1::dma::RX_FIFO_CLR_W
- spi1::dma::RX_FIFO_CNT_R
- spi1::dma::RX_FIFO_LVL_R
- spi1::dma::RX_FIFO_LVL_W
- spi1::dma::TX_DMA_EN_R
- spi1::dma::TX_DMA_EN_W
- spi1::dma::TX_FIFO_CLR_W
- spi1::dma::TX_FIFO_CNT_R
- spi1::dma::TX_FIFO_LVL_R
- spi1::dma::TX_FIFO_LVL_W
- spi1::dma::W
- spi1::i2s_ctrl::I2S_EN_R
- spi1::i2s_ctrl::I2S_EN_W
- spi1::i2s_ctrl::I2S_LJ_R
- spi1::i2s_ctrl::I2S_LJ_W
- spi1::i2s_ctrl::I2S_MONO_R
- spi1::i2s_ctrl::I2S_MONO_W
- spi1::i2s_ctrl::I2S_MUTE_R
- spi1::i2s_ctrl::I2S_MUTE_W
- spi1::i2s_ctrl::I2S_PAUSE_R
- spi1::i2s_ctrl::I2S_PAUSE_W
- spi1::i2s_ctrl::R
- spi1::i2s_ctrl::W
- spi1::int_fl::ABT_R
- spi1::int_fl::ABT_W
- spi1::int_fl::COL_R
- spi1::int_fl::COL_W
- spi1::int_fl::IRQ_R
- spi1::int_fl::IRQ_W
- spi1::int_fl::R
- spi1::int_fl::ROVR_R
- spi1::int_fl::ROVR_W
- spi1::int_fl::SLAS_R
- spi1::int_fl::TOVR_R
- spi1::int_fl::TOVR_W
- spi1::int_fl::TUND_R
- spi1::int_fl::TUND_W
- spi1::int_fl::TXST_R
- spi1::int_fl::W
- spi1::mode::NUMBITS_R
- spi1::mode::NUMBITS_W
- spi1::mode::R
- spi1::mode::SSV_R
- spi1::mode::SSV_W
- spi1::mode::SS_IO_R
- spi1::mode::SS_IO_W
- spi1::mode::TX_LJ_R
- spi1::mode::TX_LJ_W
- spi1::mode::W
- tmr0::CMP
- tmr0::CN
- tmr0::CNT
- tmr0::INTR
- tmr0::PWM
- tmr0::cmp::COMPARE_R
- tmr0::cmp::COMPARE_W
- tmr0::cmp::R
- tmr0::cmp::W
- tmr0::cn::NOLHPOL_R
- tmr0::cn::NOLHPOL_W
- tmr0::cn::NOLLPOL_R
- tmr0::cn::NOLLPOL_W
- tmr0::cn::PRES3_R
- tmr0::cn::PRES3_W
- tmr0::cn::PRES_R
- tmr0::cn::PRES_W
- tmr0::cn::PWMCKBD_R
- tmr0::cn::PWMCKBD_W
- tmr0::cn::PWMSYNC_R
- tmr0::cn::PWMSYNC_W
- tmr0::cn::R
- tmr0::cn::TEN_R
- tmr0::cn::TEN_W
- tmr0::cn::TMODE_R
- tmr0::cn::TMODE_W
- tmr0::cn::TPOL_R
- tmr0::cn::TPOL_W
- tmr0::cn::W
- tmr0::cnt::COUNT_R
- tmr0::cnt::COUNT_W
- tmr0::cnt::R
- tmr0::cnt::W
- tmr0::intr::IRQ_R
- tmr0::intr::IRQ_W
- tmr0::intr::R
- tmr0::intr::W
- tmr0::pwm::PWM_R
- tmr0::pwm::PWM_W
- tmr0::pwm::R
- tmr0::pwm::W
- uart0::BAUD0
- uart0::BAUD1
- uart0::CTRL0
- uart0::CTRL1
- uart0::DMA
- uart0::FIFO
- uart0::INT_EN
- uart0::INT_FL
- uart0::STAT
- uart0::TXFIFO
- uart0::baud0::CLKDIV_R
- uart0::baud0::CLKDIV_W
- uart0::baud0::IBAUD_R
- uart0::baud0::IBAUD_W
- uart0::baud0::R
- uart0::baud0::W
- uart0::baud1::DBAUD_R
- uart0::baud1::DBAUD_W
- uart0::baud1::R
- uart0::baud1::W
- uart0::ctrl0::BITACC_R
- uart0::ctrl0::BITACC_W
- uart0::ctrl0::BREAK_R
- uart0::ctrl0::BREAK_W
- uart0::ctrl0::CLK_SEL_R
- uart0::ctrl0::CLK_SEL_W
- uart0::ctrl0::ENABLED_R
- uart0::ctrl0::ENABLED_W
- uart0::ctrl0::FLOWPOL_R
- uart0::ctrl0::FLOWPOL_W
- uart0::ctrl0::FLOW_R
- uart0::ctrl0::FLOW_W
- uart0::ctrl0::NULLMOD_R
- uart0::ctrl0::NULLMOD_W
- uart0::ctrl0::PARITY_EN_R
- uart0::ctrl0::PARITY_EN_W
- uart0::ctrl0::PARITY_LVL_R
- uart0::ctrl0::PARITY_LVL_W
- uart0::ctrl0::PARITY_MODE_R
- uart0::ctrl0::PARITY_MODE_W
- uart0::ctrl0::R
- uart0::ctrl0::RXFLUSH_R
- uart0::ctrl0::RXFLUSH_W
- uart0::ctrl0::SIZE_R
- uart0::ctrl0::SIZE_W
- uart0::ctrl0::STOP_R
- uart0::ctrl0::STOP_W
- uart0::ctrl0::TO_CNT_R
- uart0::ctrl0::TO_CNT_W
- uart0::ctrl0::TXFLUSH_R
- uart0::ctrl0::TXFLUSH_W
- uart0::ctrl0::W
- uart0::ctrl1::R
- uart0::ctrl1::RTS_FIFO_LVL_R
- uart0::ctrl1::RTS_FIFO_LVL_W
- uart0::ctrl1::RX_FIFO_LVL_R
- uart0::ctrl1::RX_FIFO_LVL_W
- uart0::ctrl1::TX_FIFO_LVL_R
- uart0::ctrl1::TX_FIFO_LVL_W
- uart0::ctrl1::W
- uart0::dma::R
- uart0::dma::RXDMA_EN_R
- uart0::dma::RXDMA_EN_W
- uart0::dma::RXDMA_LVL_R
- uart0::dma::RXDMA_LVL_W
- uart0::dma::TXDMA_EN_R
- uart0::dma::TXDMA_EN_W
- uart0::dma::TXDMA_LVL_R
- uart0::dma::TXDMA_LVL_W
- uart0::dma::W
- uart0::fifo::FIFO_R
- uart0::fifo::FIFO_W
- uart0::fifo::R
- uart0::fifo::W
- uart0::int_en::BREAK_R
- uart0::int_en::BREAK_W
- uart0::int_en::CTS_R
- uart0::int_en::CTS_W
- uart0::int_en::LAST_BREAK_R
- uart0::int_en::LAST_BREAK_W
- uart0::int_en::R
- uart0::int_en::RX_FIFO_LVL_R
- uart0::int_en::RX_FIFO_LVL_W
- uart0::int_en::RX_FRAME_ERROR_R
- uart0::int_en::RX_FRAME_ERROR_W
- uart0::int_en::RX_OVERRUN_R
- uart0::int_en::RX_OVERRUN_W
- uart0::int_en::RX_PARITY_ERROR_R
- uart0::int_en::RX_PARITY_ERROR_W
- uart0::int_en::RX_TO_R
- uart0::int_en::RX_TO_W
- uart0::int_en::TX_FIFO_AE_R
- uart0::int_en::TX_FIFO_AE_W
- uart0::int_en::TX_FIFO_LVL_R
- uart0::int_en::TX_FIFO_LVL_W
- uart0::int_en::W
- uart0::int_fl::BREAK_R
- uart0::int_fl::BREAK_W
- uart0::int_fl::CTS_R
- uart0::int_fl::CTS_W
- uart0::int_fl::FRAME_R
- uart0::int_fl::FRAME_W
- uart0::int_fl::LAST_BREAK_R
- uart0::int_fl::LAST_BREAK_W
- uart0::int_fl::PARITY_R
- uart0::int_fl::PARITY_W
- uart0::int_fl::R
- uart0::int_fl::RX_FIFO_LVL_R
- uart0::int_fl::RX_FIFO_LVL_W
- uart0::int_fl::RX_OVR_R
- uart0::int_fl::RX_OVR_W
- uart0::int_fl::RX_TO_R
- uart0::int_fl::RX_TO_W
- uart0::int_fl::TX_FIFO_AE_R
- uart0::int_fl::TX_FIFO_AE_W
- uart0::int_fl::TX_FIFO_LVL_R
- uart0::int_fl::TX_FIFO_LVL_W
- uart0::int_fl::W
- uart0::stat::BREAK_R
- uart0::stat::PARITY_R
- uart0::stat::R
- uart0::stat::RX_BUSY_R
- uart0::stat::RX_EMPTY_R
- uart0::stat::RX_FULL_R
- uart0::stat::RX_NUM_R
- uart0::stat::RX_TO_R
- uart0::stat::TX_BUSY_R
- uart0::stat::TX_EMPTY_R
- uart0::stat::TX_FULL_R
- uart0::stat::TX_NUM_R
- uart0::txfifo::DATA_R
- uart0::txfifo::DATA_W
- uart0::txfifo::R
- uart0::txfifo::W
- wdt0::CTRL
- wdt0::RST
- wdt0::ctrl::INT_EN_R
- wdt0::ctrl::INT_EN_W
- wdt0::ctrl::INT_FLAG_R
- wdt0::ctrl::INT_FLAG_W
- wdt0::ctrl::INT_PERIOD_R
- wdt0::ctrl::INT_PERIOD_W
- wdt0::ctrl::R
- wdt0::ctrl::RST_EN_R
- wdt0::ctrl::RST_EN_W
- wdt0::ctrl::RST_FLAG_R
- wdt0::ctrl::RST_FLAG_W
- wdt0::ctrl::RST_PERIOD_R
- wdt0::ctrl::RST_PERIOD_W
- wdt0::ctrl::W
- wdt0::ctrl::WDT_EN_R
- wdt0::ctrl::WDT_EN_W
- wdt0::rst::W
- wdt0::rst::WDT_RST_W