Crate max32660

source ·
Expand description

Peripheral access API for MAX32660 microcontrollers (generated using svd2rust v0.30.1 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

  • pub use self::i2c0 as i2c1;
  • pub use self::tmr0 as tmr1;
  • pub use self::tmr0 as tmr2;
  • pub use self::uart0 as uart1;

Modules§

  • Direct Memory Access Controller.
  • Function Control.
  • Flash Memory Control.
  • Global Control Registers.
  • Common register and bit access and modify traits
  • General Purpose I/O.
  • Inter-Integrated Circuit 0.
  • Instruction Cache Controller.
  • Power Sequencer.
  • Real Time Clock.
  • System Initialization.
  • Serial Peripheral Interface 0.
  • Serial Peripheral Interface 1.
  • Low-Power Configurable Timer 0.
  • Universal Asynchronous Receiver/Transmitter 0.
  • Watchdog Timer 0.

Structs§

  • Cache and branch predictor maintenance operations
  • CPUID
  • Core peripherals
  • Debug Control Block
  • Direct Memory Access Controller.
  • Data Watchpoint and Trace unit
  • Function Control.
  • Flash Memory Control.
  • Flash Patch and Breakpoint unit
  • Floating Point Unit
  • Global Control Registers.
  • General Purpose I/O.
  • Inter-Integrated Circuit 0.
  • Inter-Integrated Circuit 1.
  • Instruction Cache Controller.
  • Instrumentation Trace Macrocell
  • Memory Protection Unit
  • Nested Vector Interrupt Controller
  • Power Sequencer.
  • All the peripherals.
  • Real Time Clock.
  • System Control Block
  • System Initialization.
  • Serial Peripheral Interface 0.
  • Serial Peripheral Interface 1.
  • SysTick: System Timer
  • Low-Power Configurable Timer 0.
  • Low-Power Configurable Timer 1.
  • Low-Power Configurable Timer 2.
  • Trace Port Interface Unit
  • Universal Asynchronous Receiver/Transmitter 0.
  • Universal Asynchronous Receiver/Transmitter 1.
  • Watchdog Timer 0.

Enums§

Constants§