Crate max32660_pac

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Peripheral access API for MAX32660 microcontrollers (generated using svd2rust v0.21.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use i2c0 as i2c1;
pub use icc0 as icc1;
pub use tmr0 as tmr1;
pub use tmr0 as tmr2;
pub use uart0 as uart1;

Modules§

bbfc
Battery-Backed Function Control.
bbsir
Battery-Backed Registers.
dma
DMA Controller Fully programmable, chaining capable DMA channels.
flc
Flash Memory Control.
gcr
Global Control Registers.
generic
Common register and bit access and modify traits
gpio0
Individual I/O for each GPIO
i2c0
Inter-Integrated Circuit.
icc0
Instruction Cache Controller Registers
pwrseq
Power Sequencer / Low Power Control Register.
rtc
Real Time Clock and Alarm.
sir
System Initialization Registers.
smon
The Security Monitor block used to monitor system threat conditions.
spi17y
SPI peripheral.
spimss
Serial Peripheral Interface.
tmr0
32-bit reloadable timer that can be used for timing and event counting.
uart0
UART
wdt0
Watchdog Timer 0

Structs§

BBFC
Battery-Backed Function Control.
BBSIR
Battery-Backed Registers.
CBP
Cache and branch predictor maintenance operations
CPUID
CPUID
CorePeripherals
Core peripherals
DCB
Debug Control Block
DMA
DMA Controller Fully programmable, chaining capable DMA channels.
DWT
Data Watchpoint and Trace unit
FLC
Flash Memory Control.
FPB
Flash Patch and Breakpoint unit
FPU
Floating Point Unit
GCR
Global Control Registers.
GPIO0
Individual I/O for each GPIO
I2C0
Inter-Integrated Circuit.
I2C1
Inter-Integrated Circuit. 1
ICC0
Instruction Cache Controller Registers
ICC1
Instruction Cache Controller Registers 1
ITM
Instrumentation Trace Macrocell
MPU
Memory Protection Unit
NVIC
Nested Vector Interrupt Controller
PWRSEQ
Power Sequencer / Low Power Control Register.
Peripherals
All the peripherals
RTC
Real Time Clock and Alarm.
SCB
System Control Block
SIR
System Initialization Registers.
SMON
The Security Monitor block used to monitor system threat conditions.
SPI17Y
SPI peripheral.
SPIMSS
Serial Peripheral Interface.
SYST
SysTick: System Timer
TMR0
32-bit reloadable timer that can be used for timing and event counting.
TMR1
32-bit reloadable timer that can be used for timing and event counting. 1
TMR2
32-bit reloadable timer that can be used for timing and event counting. 2
TPIU
Trace Port Interface Unit
UART0
UART
UART1
UART 1
WDT0
Watchdog Timer 0

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS
Number available in the NVIC for configuring priority