lpc8xx_hal/dma/
gen.rs

1use crate::{
2    init_state::{Disabled, Enabled},
3    pac::{
4        self,
5        dma0::channel::{CFG, XFERCFG},
6    },
7    reg_proxy::RegProxy,
8};
9
10use super::{
11    channels::{self, Channel},
12    descriptors::DescriptorTable,
13};
14
15macro_rules! channels {
16    ($($field:ident, $name:ident, $index:expr, $cfg:ident, $xfercfg:ident;)*) => {
17        /// Provides access to all channels
18        ///
19        /// This struct is part of the [`DMA`] struct.
20        ///
21        /// [`DMA`]: struct.DMA.html
22        #[allow(missing_docs)]
23        pub struct Channels<State> {
24            $(pub $field: Channel<$name, State>,)*
25        }
26
27        impl Channels<Disabled> {
28            pub(super) fn new(descriptors: &'static mut DescriptorTable)
29                -> Self
30            {
31                let mut descriptors = (&mut descriptors.0).into_iter();
32
33                Channels {
34                    $(
35                        $field: Channel {
36                            ty        : $name(()),
37                            _state    : Disabled,
38                            descriptor: descriptors.next().unwrap(),
39
40                            cfg    : RegProxy::new(),
41                            xfercfg: RegProxy::new(),
42                        },
43                    )*
44                }
45            }
46
47            pub(super) fn enable(self) -> Channels<Enabled> {
48                Channels {
49                    $(
50                        $field: self.$field.enable(),
51                    )*
52                }
53            }
54        }
55
56        impl Channels<Enabled> {
57            pub(super) fn disable(self) -> Channels<Disabled> {
58                Channels {
59                    $(
60                        $field: self.$field.disable(),
61                    )*
62                }
63            }
64        }
65
66
67        $(
68            /// This struct is an internal implementation detail
69            pub struct $xfercfg;
70
71            reg_cluster!($xfercfg, XFERCFG, pac::DMA0, $field, xfercfg);
72
73            /// This struct is an interal implementation detail
74            pub struct $cfg;
75
76            reg_cluster!($cfg, CFG, pac::DMA0, $field, cfg);
77
78            /// Identifies a DMA channel
79            pub struct $name(());
80
81            impl channels::Instance for $name {
82                const INDEX: usize = $index;
83                const FLAG : u32   = 0x1 << Self::INDEX;
84
85                type Cfg     = $cfg;
86                type Xfercfg = $xfercfg;
87            }
88        )*
89    }
90}
91
92#[cfg(feature = "82x")]
93// The channels must always be specified in order, from lowest to highest, as
94// the channel descriptors are assigned based on that order.
95channels!(
96    channel0 , Channel0 ,  0, CFG0 , XFERCFG0 ;
97    channel1 , Channel1 ,  1, CFG1 , XFERCFG1 ;
98    channel2 , Channel2 ,  2, CFG2 , XFERCFG2 ;
99    channel3 , Channel3 ,  3, CFG3 , XFERCFG3 ;
100    channel4 , Channel4 ,  4, CFG4 , XFERCFG4 ;
101    channel5 , Channel5 ,  5, CFG5 , XFERCFG5 ;
102    channel6 , Channel6 ,  6, CFG6 , XFERCFG6 ;
103    channel7 , Channel7 ,  7, CFG7 , XFERCFG7 ;
104    channel8 , Channel8 ,  8, CFG8 , XFERCFG8 ;
105    channel9 , Channel9 ,  9, CFG9 , XFERCFG9 ;
106    channel10, Channel10, 10, CFG10, XFERCFG10;
107    channel11, Channel11, 11, CFG11, XFERCFG11;
108    channel12, Channel12, 12, CFG12, XFERCFG12;
109    channel13, Channel13, 13, CFG13, XFERCFG13;
110    channel14, Channel14, 14, CFG14, XFERCFG14;
111    channel15, Channel15, 15, CFG15, XFERCFG15;
112    channel16, Channel16, 16, CFG16, XFERCFG16;
113    channel17, Channel17, 17, CFG17, XFERCFG17;
114);
115
116#[cfg(feature = "845")]
117// The channels must always be specified in order, from lowest to highest, as
118// the channel descriptors are assigned based on that order.
119channels!(
120    channel0 , Channel0 ,  0, CFG0 , XFERCFG0 ;
121    channel1 , Channel1 ,  1, CFG1 , XFERCFG1 ;
122    channel2 , Channel2 ,  2, CFG2 , XFERCFG2 ;
123    channel3 , Channel3 ,  3, CFG3 , XFERCFG3 ;
124    channel4 , Channel4 ,  4, CFG4 , XFERCFG4 ;
125    channel5 , Channel5 ,  5, CFG5 , XFERCFG5 ;
126    channel6 , Channel6 ,  6, CFG6 , XFERCFG6 ;
127    channel7 , Channel7 ,  7, CFG7 , XFERCFG7 ;
128    channel8 , Channel8 ,  8, CFG8 , XFERCFG8 ;
129    channel9 , Channel9 ,  9, CFG9 , XFERCFG9 ;
130    channel10, Channel10, 10, CFG10, XFERCFG10;
131    channel11, Channel11, 11, CFG11, XFERCFG11;
132    channel12, Channel12, 12, CFG12, XFERCFG12;
133    channel13, Channel13, 13, CFG13, XFERCFG13;
134    channel14, Channel14, 14, CFG14, XFERCFG14;
135    channel15, Channel15, 15, CFG15, XFERCFG15;
136    channel16, Channel16, 16, CFG16, XFERCFG16;
137    channel17, Channel17, 17, CFG17, XFERCFG17;
138    channel18, Channel18, 18, CFG18, XFERCFG18;
139    channel19, Channel19, 19, CFG19, XFERCFG19;
140    channel20, Channel20, 20, CFG20, XFERCFG20;
141    channel21, Channel21, 21, CFG21, XFERCFG21;
142    channel22, Channel22, 22, CFG22, XFERCFG22;
143    channel23, Channel23, 23, CFG23, XFERCFG23;
144    channel24, Channel24, 24, CFG24, XFERCFG24;
145);
lpc8xx_hal/dma/gen.rs

lpc8xx_hal/dma/
gen.rs
