Module lpc845_pac::dma0::channel::xfercfg [−][src]
Expand description
Transfer configuration register for DMA channel .
Structs
Field CFGVALID reader - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
Field CFGVALID writer - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
Field CLRTRIG reader - Clear Trigger.
Field CLRTRIG writer - Clear Trigger.
Field DSTINC reader - Determines whether the destination address is incremented for each DMA transfer.
Field DSTINC writer - Determines whether the destination address is incremented for each DMA transfer.
Register XFERCFG reader
Field RELOAD reader - Indicates whether the channel’s control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
Field RELOAD writer - Indicates whether the channel’s control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
Field SETINTA reader - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
Field SETINTA writer - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
Field SETINTB reader - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
Field SETINTB writer - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
Field SRCINC reader - Determines whether the source address is incremented for each DMA transfer.
Field SRCINC writer - Determines whether the source address is incremented for each DMA transfer.
Field SWTRIG reader - Software Trigger.
Field SWTRIG writer - Software Trigger.
Register XFERCFG writer
Field WIDTH reader - Transfer width used for this DMA channel.
Field WIDTH writer - Transfer width used for this DMA channel.
Transfer configuration register for DMA channel .
Field XFERCOUNT reader - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed.
Field XFERCOUNT writer - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed.
Enums
Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
Clear Trigger.
Determines whether the destination address is incremented for each DMA transfer.
Indicates whether the channel’s control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
Determines whether the source address is incremented for each DMA transfer.
Software Trigger.
Transfer width used for this DMA channel.