Module lpc845_pac::dma0::channel::cfg [−][src]
Expand description
Configuration register for DMA channel .
Structs
Field BURSTPOWER reader - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
Field BURSTPOWER writer - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size.
Configuration register for DMA channel .
Field CHPRIORITY reader - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
Field CHPRIORITY writer - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
Field DSTBURSTWRAP reader - Destination Burst Wrap. When enabled, the destination data address for the DMA is ‘wrapped’, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
Field DSTBURSTWRAP writer - Destination Burst Wrap. When enabled, the destination data address for the DMA is ‘wrapped’, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
Field HWTRIGEN reader - Hardware Triggering Enable for this channel.
Field HWTRIGEN writer - Hardware Triggering Enable for this channel.
Field PERIPHREQEN reader - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
Field PERIPHREQEN writer - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
Register CFG reader
Field SRCBURSTWRAP reader - Source Burst Wrap. When enabled, the source data address for the DMA is ‘wrapped’, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
Field SRCBURSTWRAP writer - Source Burst Wrap. When enabled, the source data address for the DMA is ‘wrapped’, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
Field TRIGBURST reader - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
Field TRIGBURST writer - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
Field TRIGPOL reader - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
Field TRIGPOL writer - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
Field TRIGTYPE reader - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
Field TRIGTYPE writer - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
Register CFG writer
Enums
Destination Burst Wrap. When enabled, the destination data address for the DMA is ‘wrapped’, meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.
Hardware Triggering Enable for this channel.
Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.
Source Burst Wrap. When enabled, the source data address for the DMA is ‘wrapped’, meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.
Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
Trigger Type. Selects hardware trigger as edge triggered or level triggered.