Module lpc845_pac::sct0::event::ctrl [−][src]
Expand description
SCT event control register 0
Structs
Field COMBMODE reader - Selects how the specified match and I/O condition are used and combined.
Field COMBMODE writer - Selects how the specified match and I/O condition are used and combined.
SCT event control register 0
Field DIRECTION reader - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
Field DIRECTION writer - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
Field HEVENT reader - Select L/H counter. Do not set this bit if UNIFY = 1.
Field HEVENT writer - Select L/H counter. Do not set this bit if UNIFY = 1.
Field IOCOND reader - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
Field IOCOND writer - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
Field IOSEL reader - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
Field IOSEL writer - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event.
Field MATCHMEM reader - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
Field MATCHMEM writer - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value.
Field MATCHSEL reader - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
Field MATCHSEL writer - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running.
Field OUTSEL reader - Input/output select
Field OUTSEL writer - Input/output select
Register CTRL reader
Field STATELD reader - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
Field STATELD writer - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.
Field STATEV reader - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
Field STATEV writer - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value.
Register CTRL writer
Enums
Selects how the specified match and I/O condition are used and combined.
Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
Select L/H counter. Do not set this bit if UNIFY = 1.
Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .
Input/output select
This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.