[−][src]Module lpc845_pac::syscon
LPC84x System configuration (SYSCON)
Modules
| adcclkdiv | ADC clock divider register |
| adcclksel | ADC clock source select register |
| bodctrl | BOD control register |
| captclksel | CAPT clock source select register |
| clkoutdiv | CLKOUT clock divider registers |
| clkoutsel | CLKOUT clock source select register |
| device_id | Part ID register |
| extclksel | external clock source select register |
| exttracecmd | External trace buffer command register |
| fclksel | peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. |
| frg | Register block no description available |
| frodirectclkuen | FRO direct clock source update enable register |
| frooscctrl | FRO oscillator control |
| ioconclkdiv0 | Peripheral clock 0 to the IOCON block for programmable glitch filter |
| ioconclkdiv1 | Peripheral clock 1 to the IOCON block for programmable glitch filter |
| ioconclkdiv2 | Peripheral clock 2 to the IOCON block for programmable glitch filter |
| ioconclkdiv3 | Peripheral clock 3 to the IOCON block for programmable glitch filter |
| ioconclkdiv4 | Peripheral clock 4 to the IOCON block for programmable glitch filter |
| ioconclkdiv5 | Peripheral clock 6 to the IOCON block for programmable glitch filter |
| ioconclkdiv6 | Peripheral clock 6 to the IOCON block for programmable glitch filter |
| irqlatency | IRQ latency register |
| mainclkpllsel | Main clock source select register |
| mainclkplluen | Main clock source update enable register |
| mainclksel | Main clock source select register |
| mainclkuen | Main clock source update enable register |
| nmisrc | NMI source selection register |
| pdawakecfg | Wake-up configuration register |
| pdruncfg | Power configuration register |
| pdsleepcfg | Deep-sleep configuration register |
| pintsel | Pin interrupt select registers N |
| pioporcap | POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs) |
| presetctrl0 | Peripheral reset group 0 control register |
| presetctrl1 | Peripheral reset group 1 control register |
| sctclkdiv | SCT clock divider register |
| sctclksel | SCT clock source select register |
| starterp0 | Start logic 0 pin wake-up enable register 0 |
| starterp1 | Start logic 0 pin wake-up enable register 1 |
| sysahbclkctrl0 | System clock group 0 control register |
| sysahbclkctrl1 | System clock group 1 control register |
| sysahbclkdiv | System clock divider register |
| sysmemremap | System Remap register |
| sysoscctrl | system oscillator control |
| syspllclksel | System PLL clock source select register |
| syspllclkuen | System PLL clock source update enable register |
| syspllctrl | PLL control |
| syspllstat | PLL status |
| sysrststat | System reset status register |
| systckcal | System tick timer calibration register |
| wdtoscctrl | Watchdog oscillator control |
Structs
| FRG | Register block |
| RegisterBlock | Register block |
Type Definitions
| ADCCLKDIV | ADC clock divider register |
| ADCCLKSEL | ADC clock source select register |
| BODCTRL | BOD control register |
| CAPTCLKSEL | CAPT clock source select register |
| CLKOUTDIV | CLKOUT clock divider registers |
| CLKOUTSEL | CLKOUT clock source select register |
| DEVICE_ID | Part ID register |
| EXTCLKSEL | external clock source select register |
| EXTTRACECMD | External trace buffer command register |
| FCLKSEL | peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register. |
| FRODIRECTCLKUEN | FRO direct clock source update enable register |
| FROOSCCTRL | FRO oscillator control |
| IOCONCLKDIV0 | Peripheral clock 0 to the IOCON block for programmable glitch filter |
| IOCONCLKDIV1 | Peripheral clock 1 to the IOCON block for programmable glitch filter |
| IOCONCLKDIV2 | Peripheral clock 2 to the IOCON block for programmable glitch filter |
| IOCONCLKDIV3 | Peripheral clock 3 to the IOCON block for programmable glitch filter |
| IOCONCLKDIV4 | Peripheral clock 4 to the IOCON block for programmable glitch filter |
| IOCONCLKDIV5 | Peripheral clock 6 to the IOCON block for programmable glitch filter |
| IOCONCLKDIV6 | Peripheral clock 6 to the IOCON block for programmable glitch filter |
| IRQLATENCY | IRQ latency register |
| MAINCLKPLLSEL | Main clock source select register |
| MAINCLKPLLUEN | Main clock source update enable register |
| MAINCLKSEL | Main clock source select register |
| MAINCLKUEN | Main clock source update enable register |
| NMISRC | NMI source selection register |
| PDAWAKECFG | Wake-up configuration register |
| PDRUNCFG | Power configuration register |
| PDSLEEPCFG | Deep-sleep configuration register |
| PINTSEL | Pin interrupt select registers N |
| PIOPORCAP | POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs) |
| PRESETCTRL0 | Peripheral reset group 0 control register |
| PRESETCTRL1 | Peripheral reset group 1 control register |
| SCTCLKDIV | SCT clock divider register |
| SCTCLKSEL | SCT clock source select register |
| STARTERP0 | Start logic 0 pin wake-up enable register 0 |
| STARTERP1 | Start logic 0 pin wake-up enable register 1 |
| SYSAHBCLKCTRL0 | System clock group 0 control register |
| SYSAHBCLKCTRL1 | System clock group 1 control register |
| SYSAHBCLKDIV | System clock divider register |
| SYSMEMREMAP | System Remap register |
| SYSOSCCTRL | system oscillator control |
| SYSPLLCLKSEL | System PLL clock source select register |
| SYSPLLCLKUEN | System PLL clock source update enable register |
| SYSPLLCTRL | PLL control |
| SYSPLLSTAT | PLL status |
| SYSRSTSTAT | System reset status register |
| SYSTCKCAL | System tick timer calibration register |
| WDTOSCCTRL | Watchdog oscillator control |