Module lpc82x::dma

DMA controller

Modules

abort0	Channel Abort control for all DMA channels.
active0	Channel Active status for all DMA channels.
busy0	Channel Busy status for all DMA channels.
cfg	Configuration register for DMA channel 0.
ctlstat	Control and status register for DMA channel 0.
ctrl	DMA control.
enableclr0	Channel Enable Clear for all DMA channels.
enableset0	Channel Enable read and Set for all DMA channels.
errint0	Error Interrupt status for all DMA channels.
inta0	Interrupt A status for all DMA channels.
intb0	Interrupt B status for all DMA channels.
intenclr0	Interrupt Enable Clear for all DMA channels.
intenset0	Interrupt Enable read and Set for all DMA channels.
intstat	Interrupt status.
settrig0	Set Trigger control bits for all DMA channels.
setvalid0	Set ValidPending control bits for all DMA channels.
srambase	SRAM address of the channel configuration table.
xfercfg	Transfer configuration register for DMA channel 0.

Structs

ABORT0	Channel Abort control for all DMA channels.
ACTIVE0	Channel Active status for all DMA channels.
BUSY0	Channel Busy status for all DMA channels.
CFG	Configuration register for DMA channel 0.
CTLSTAT	Control and status register for DMA channel 0.
CTRL	DMA control.
ENABLECLR0	Channel Enable Clear for all DMA channels.
ENABLESET0	Channel Enable read and Set for all DMA channels.
ERRINT0	Error Interrupt status for all DMA channels.
INTA0	Interrupt A status for all DMA channels.
INTB0	Interrupt B status for all DMA channels.
INTENCLR0	Interrupt Enable Clear for all DMA channels.
INTENSET0	Interrupt Enable read and Set for all DMA channels.
INTSTAT	Interrupt status.
RegisterBlock	Register block
SETTRIG0	Set Trigger control bits for all DMA channels.
SETVALID0	Set ValidPending control bits for all DMA channels.
SRAMBASE	SRAM address of the channel configuration table.
XFERCFG	Transfer configuration register for DMA channel 0.