Struct lpc82x::sct::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub config: CONFIG,
    pub ctrl: CTRL,
    pub limit: LIMIT,
    pub halt: HALT,
    pub stop: STOP,
    pub start: START,
    pub count: COUNT,
    pub state: STATE,
    pub input: INPUT,
    pub regmode: REGMODE,
    pub output: OUTPUT,
    pub outputdirctrl: OUTPUTDIRCTRL,
    pub res: RES,
    pub dmareq0: DMAREQ0,
    pub dmareq1: DMAREQ1,
    pub even: EVEN,
    pub evflag: EVFLAG,
    pub conen: CONEN,
    pub conflag: CONFLAG,
    pub match_: [MATCH; 8],
    pub matchrel: [MATCHREL; 8],
    pub ev0_state: EV_STATE,
    pub ev0_ctrl: EV_CTRL,
    pub ev1_state: EV_STATE,
    pub ev1_ctrl: EV_CTRL,
    pub ev2_state: EV_STATE,
    pub ev2_ctrl: EV_CTRL,
    pub ev3_state: EV_STATE,
    pub ev3_ctrl: EV_CTRL,
    pub ev4_state: EV_STATE,
    pub ev4_ctrl: EV_CTRL,
    pub ev5_state: EV_STATE,
    pub ev5_ctrl: EV_CTRL,
    pub ev6_state: EV_STATE,
    pub ev6_ctrl: EV_CTRL,
    pub ev7_state: EV_STATE,
    pub ev7_ctrl: EV_CTRL,
    pub out0_set: OUT_SET,
    pub out0_clr: OUT_CLR,
    pub out1_set: OUT_SET,
    pub out1_clr: OUT_CLR,
    pub out2_set: OUT_SET,
    pub out2_clr: OUT_CLR,
    pub out3_set: OUT_SET,
    pub out3_clr: OUT_CLR,
    pub out4_set: OUT_SET,
    pub out4_clr: OUT_CLR,
    pub out5_set: OUT_SET,
    pub out5_clr: OUT_CLR,
    // some fields omitted
}

Register block

Fields

config: CONFIG

0x00 - SCT configuration register

ctrl: CTRL

0x04 - SCT control register

limit: LIMIT

0x08 - SCT limit register

halt: HALT

0x0c - SCT halt condition register

stop: STOP

0x10 - SCT stop condition register

start: START

0x14 - SCT start condition register

count: COUNT

0x40 - SCT counter register

state: STATE

0x44 - SCT state register

input: INPUT

0x48 - SCT input register

regmode: REGMODE

0x4c - SCT match/capture registers mode register

output: OUTPUT

0x50 - SCT output register

outputdirctrl: OUTPUTDIRCTRL

0x54 - SCT output counter direction control register

res: RES

0x58 - SCT conflict resolution register

dmareq0: DMAREQ0

0x5c - SCT DMA request 0 register

dmareq1: DMAREQ1

0x60 - SCT DMA request 1 register

even: EVEN

0xf0 - SCT event enable register

evflag: EVFLAG

0xf4 - SCT event flag register

conen: CONEN

0xf8 - SCT conflict enable register

conflag: CONFLAG

0xfc - SCT conflict flag register

match_: [MATCH; 8]

0x100 - SCT match value register of match channels 0 to 7; REGMOD0 to REGMODE7 = 0

matchrel: [MATCHREL; 8]

0x200 - SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7 = 0

ev0_state: EV_STATE

0x300 - SCT event state register 0

ev0_ctrl: EV_CTRL

0x304 - SCT event control register 0

ev1_state: EV_STATE

0x308 - SCT event state register 0

ev1_ctrl: EV_CTRL

0x30c - SCT event control register 0

ev2_state: EV_STATE

0x310 - SCT event state register 0

ev2_ctrl: EV_CTRL

0x314 - SCT event control register 0

ev3_state: EV_STATE

0x318 - SCT event state register 0

ev3_ctrl: EV_CTRL

0x31c - SCT event control register 0

ev4_state: EV_STATE

0x320 - SCT event state register 0

ev4_ctrl: EV_CTRL

0x324 - SCT event control register 0

ev5_state: EV_STATE

0x328 - SCT event state register 0

ev5_ctrl: EV_CTRL

0x32c - SCT event control register 0

ev6_state: EV_STATE

0x330 - SCT event state register 0

ev6_ctrl: EV_CTRL

0x334 - SCT event control register 0

ev7_state: EV_STATE

0x338 - SCT event state register 0

ev7_ctrl: EV_CTRL

0x33c - SCT event control register 0

out0_set: OUT_SET

0x500 - SCT output 0 set register

out0_clr: OUT_CLR

0x504 - SCT output 0 clear register

out1_set: OUT_SET

0x508 - SCT output 0 set register

out1_clr: OUT_CLR

0x50c - SCT output 0 clear register

out2_set: OUT_SET

0x510 - SCT output 0 set register

out2_clr: OUT_CLR

0x514 - SCT output 0 clear register

out3_set: OUT_SET

0x518 - SCT output 0 set register

out3_clr: OUT_CLR

0x51c - SCT output 0 clear register

out4_set: OUT_SET

0x520 - SCT output 0 set register

out4_clr: OUT_CLR

0x524 - SCT output 0 clear register

out5_set: OUT_SET

0x528 - SCT output 0 set register

out5_clr: OUT_CLR

0x52c - SCT output 0 clear register