Struct lpc82x::dma::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub ctrl: CTRL,
    pub intstat: INTSTAT,
    pub srambase: SRAMBASE,
    pub enableset0: ENABLESET0,
    pub enableclr0: ENABLECLR0,
    pub active0: ACTIVE0,
    pub busy0: BUSY0,
    pub errint0: ERRINT0,
    pub intenset0: INTENSET0,
    pub intenclr0: INTENCLR0,
    pub inta0: INTA0,
    pub intb0: INTB0,
    pub setvalid0: SETVALID0,
    pub settrig0: SETTRIG0,
    pub abort0: ABORT0,
    pub cfg0: CFG,
    pub ctlstat0: CTLSTAT,
    pub xfercfg0: XFERCFG,
    pub cfg1: CFG,
    pub ctlstat1: CTLSTAT,
    pub xfercfg1: XFERCFG,
    pub cfg2: CFG,
    pub ctlstat2: CTLSTAT,
    pub xfercfg2: XFERCFG,
    pub cfg3: CFG,
    pub ctlstat3: CTLSTAT,
    pub xfercfg3: XFERCFG,
    pub cfg4: CFG,
    pub ctlstat4: CTLSTAT,
    pub xfercfg4: XFERCFG,
    pub cfg5: CFG,
    pub ctlstat5: CTLSTAT,
    pub xfercfg5: XFERCFG,
    pub cfg6: CFG,
    pub ctlstat6: CTLSTAT,
    pub xfercfg6: XFERCFG,
    pub cfg7: CFG,
    pub ctlstat7: CTLSTAT,
    pub xfercfg7: XFERCFG,
    pub cfg8: CFG,
    pub ctlstat8: CTLSTAT,
    pub xfercfg8: XFERCFG,
    pub cfg9: CFG,
    pub ctlstat9: CTLSTAT,
    pub xfercfg9: XFERCFG,
    pub cfg10: CFG,
    pub ctlstat10: CTLSTAT,
    pub xfercfg10: XFERCFG,
    pub cfg11: CFG,
    pub ctlstat11: CTLSTAT,
    pub xfercfg11: XFERCFG,
    pub cfg12: CFG,
    pub ctlstat12: CTLSTAT,
    pub xfercfg12: XFERCFG,
    pub cfg13: CFG,
    pub ctlstat13: CTLSTAT,
    pub xfercfg13: XFERCFG,
    pub cfg14: CFG,
    pub ctlstat14: CTLSTAT,
    pub xfercfg14: XFERCFG,
    pub cfg15: CFG,
    pub ctlstat15: CTLSTAT,
    pub xfercfg15: XFERCFG,
    pub cfg16: CFG,
    pub ctlstat16: CTLSTAT,
    pub xfercfg16: XFERCFG,
    pub cfg17: CFG,
    pub ctlstat17: CTLSTAT,
    pub xfercfg17: XFERCFG,
    // some fields omitted
}

Register block

Fields

ctrl: CTRL

0x00 - DMA control.

intstat: INTSTAT

0x04 - Interrupt status.

srambase: SRAMBASE

0x08 - SRAM address of the channel configuration table.

enableset0: ENABLESET0

0x20 - Channel Enable read and Set for all DMA channels.

enableclr0: ENABLECLR0

0x28 - Channel Enable Clear for all DMA channels.

active0: ACTIVE0

0x30 - Channel Active status for all DMA channels.

busy0: BUSY0

0x38 - Channel Busy status for all DMA channels.

errint0: ERRINT0

0x40 - Error Interrupt status for all DMA channels.

intenset0: INTENSET0

0x48 - Interrupt Enable read and Set for all DMA channels.

intenclr0: INTENCLR0

0x50 - Interrupt Enable Clear for all DMA channels.

inta0: INTA0

0x58 - Interrupt A status for all DMA channels.

intb0: INTB0

0x60 - Interrupt B status for all DMA channels.

setvalid0: SETVALID0

0x68 - Set ValidPending control bits for all DMA channels.

settrig0: SETTRIG0

0x70 - Set Trigger control bits for all DMA channels.

abort0: ABORT0

0x78 - Channel Abort control for all DMA channels.

cfg0: CFG

0x400 - Configuration register for DMA channel 0.

ctlstat0: CTLSTAT

0x404 - Control and status register for DMA channel 0.

xfercfg0: XFERCFG

0x408 - Transfer configuration register for DMA channel 0.

cfg1: CFG

0x410 - Configuration register for DMA channel 0.

ctlstat1: CTLSTAT

0x414 - Control and status register for DMA channel 0.

xfercfg1: XFERCFG

0x418 - Transfer configuration register for DMA channel 0.

cfg2: CFG

0x420 - Configuration register for DMA channel 0.

ctlstat2: CTLSTAT

0x424 - Control and status register for DMA channel 0.

xfercfg2: XFERCFG

0x428 - Transfer configuration register for DMA channel 0.

cfg3: CFG

0x430 - Configuration register for DMA channel 0.

ctlstat3: CTLSTAT

0x434 - Control and status register for DMA channel 0.

xfercfg3: XFERCFG

0x438 - Transfer configuration register for DMA channel 0.

cfg4: CFG

0x440 - Configuration register for DMA channel 0.

ctlstat4: CTLSTAT

0x444 - Control and status register for DMA channel 0.

xfercfg4: XFERCFG

0x448 - Transfer configuration register for DMA channel 0.

cfg5: CFG

0x450 - Configuration register for DMA channel 0.

ctlstat5: CTLSTAT

0x454 - Control and status register for DMA channel 0.

xfercfg5: XFERCFG

0x458 - Transfer configuration register for DMA channel 0.

cfg6: CFG

0x460 - Configuration register for DMA channel 0.

ctlstat6: CTLSTAT

0x464 - Control and status register for DMA channel 0.

xfercfg6: XFERCFG

0x468 - Transfer configuration register for DMA channel 0.

cfg7: CFG

0x470 - Configuration register for DMA channel 0.

ctlstat7: CTLSTAT

0x474 - Control and status register for DMA channel 0.

xfercfg7: XFERCFG

0x478 - Transfer configuration register for DMA channel 0.

cfg8: CFG

0x480 - Configuration register for DMA channel 0.

ctlstat8: CTLSTAT

0x484 - Control and status register for DMA channel 0.

xfercfg8: XFERCFG

0x488 - Transfer configuration register for DMA channel 0.

cfg9: CFG

0x490 - Configuration register for DMA channel 0.

ctlstat9: CTLSTAT

0x494 - Control and status register for DMA channel 0.

xfercfg9: XFERCFG

0x498 - Transfer configuration register for DMA channel 0.

cfg10: CFG

0x4a0 - Configuration register for DMA channel 0.

ctlstat10: CTLSTAT

0x4a4 - Control and status register for DMA channel 0.

xfercfg10: XFERCFG

0x4a8 - Transfer configuration register for DMA channel 0.

cfg11: CFG

0x4b0 - Configuration register for DMA channel 0.

ctlstat11: CTLSTAT

0x4b4 - Control and status register for DMA channel 0.

xfercfg11: XFERCFG

0x4b8 - Transfer configuration register for DMA channel 0.

cfg12: CFG

0x4c0 - Configuration register for DMA channel 0.

ctlstat12: CTLSTAT

0x4c4 - Control and status register for DMA channel 0.

xfercfg12: XFERCFG

0x4c8 - Transfer configuration register for DMA channel 0.

cfg13: CFG

0x4d0 - Configuration register for DMA channel 0.

ctlstat13: CTLSTAT

0x4d4 - Control and status register for DMA channel 0.

xfercfg13: XFERCFG

0x4d8 - Transfer configuration register for DMA channel 0.

cfg14: CFG

0x4e0 - Configuration register for DMA channel 0.

ctlstat14: CTLSTAT

0x4e4 - Control and status register for DMA channel 0.

xfercfg14: XFERCFG

0x4e8 - Transfer configuration register for DMA channel 0.

cfg15: CFG

0x4f0 - Configuration register for DMA channel 0.

ctlstat15: CTLSTAT

0x4f4 - Control and status register for DMA channel 0.

xfercfg15: XFERCFG

0x4f8 - Transfer configuration register for DMA channel 0.

cfg16: CFG

0x500 - Configuration register for DMA channel 0.

ctlstat16: CTLSTAT

0x504 - Control and status register for DMA channel 0.

xfercfg16: XFERCFG

0x508 - Transfer configuration register for DMA channel 0.

cfg17: CFG

0x510 - Configuration register for DMA channel 0.

ctlstat17: CTLSTAT

0x514 - Control and status register for DMA channel 0.

xfercfg17: XFERCFG

0x518 - Transfer configuration register for DMA channel 0.