Module lpc82x::spi0
[−]
[src]
SPI0
Modules
cfg |
SPI Configuration register |
div |
SPI clock Divider |
dly |
SPI Delay register |
intenclr |
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. |
intenset |
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. |
intstat |
SPI Interrupt Status |
rxdat |
SPI Receive Data |
stat |
SPI Status. Some status flags can be cleared by writing a 1 to that bit position |
txctl |
SPI Transmit Control |
txdat |
SPI Transmit Data |
txdatctl |
SPI Transmit Data with Control |
Structs
CFG |
SPI Configuration register |
DIV |
SPI clock Divider |
DLY |
SPI Delay register |
INTENCLR |
SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. |
INTENSET |
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. |
INTSTAT |
SPI Interrupt Status |
RXDAT |
SPI Receive Data |
RegisterBlock |
Register block |
STAT |
SPI Status. Some status flags can be cleared by writing a 1 to that bit position |
TXCTL |
SPI Transmit Control |
TXDAT |
SPI Transmit Data |
TXDATCTL |
SPI Transmit Data with Control |