Module lpc81x_pac::lpc810::usart0

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USARTs

Modules

brg

Baud Rate Generator register. 16-bit integer baud rate divisor value.

cfg

USART Configuration register. Basic USART configuration settings that typically are not changed during operation.

ctl

USART Control register. USART control settings that are more likely to change during operation.

intenclr

Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.

intenset

Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

intstat

Interrupt status register. Reflects interrupts that are currently enabled.

rxdat

Receiver Data register. Contains the last character received.

rxdatstat

Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.

stat

USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.

txdat

Transmit Data register. Data to be transmitted is written here.