[−][src]Module lpc81x_pac::sct
State Configurable Timer (SCT)
Modules
cap | SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1 |
capctrl | SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1 |
conen | SCT conflict enable register |
config | SCT configuration register |
conflag | SCT conflict flag register |
count | SCT counter register |
ctrl | SCT control register |
ev0_ctrl | SCT event control register 0 |
ev0_state | SCT event state register 0 |
ev1_state | SCT event state register 1 |
ev1_ctrl | SCT event control register 1 |
ev2_state | SCT event state register 2 |
ev2_ctrl | SCT event control register 2 |
ev3_state | SCT event state register 3 |
ev3_ctrl | SCT event control register 3 |
ev4_state | SCT event state register 4 |
ev4_ctrl | SCT event control register 4 |
ev5_state | SCT event state register 5 |
ev5_ctrl | SCT event control register 5 |
even | SCT event enable register |
evflag | SCT event flag register |
halt | SCT halt condition register |
input | SCT input register |
limit | SCT limit register |
match_ | SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0 |
matchrel | SCT match reload value register 0 to 4 REGMOD0 = 0 to REGMODE4 = 0 |
out0_set | SCT output 0 set register |
out0_clr | SCT output 0 clear register |
out1_set | SCT output 1 set register |
out1_clr | SCT output 1 clear register |
out2_set | SCT output 2 set register |
out2_clr | SCT output 2 clear register |
out3_set | SCT output 3 set register |
out3_clr | SCT output 3 clear register |
output | SCT output register |
outputdirctrl | SCT output counter direction control register |
regmode | SCT match/capture registers mode register |
res | SCT conflict resolution register |
start | SCT start condition register |
state | SCT state register |
stop | SCT stop condition register |
Structs
CAP | SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4 = 1 |
CAPCTRL | SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4 = 1 |
CONEN | SCT conflict enable register |
CONFIG | SCT configuration register |
CONFLAG | SCT conflict flag register |
COUNT | SCT counter register |
CTRL | SCT control register |
EV0_CTRL | SCT event control register 0 |
EV0_STATE | SCT event state register 0 |
EV1_STATE | SCT event state register 1 |
EV1_CTRL | SCT event control register 1 |
EV2_STATE | SCT event state register 2 |
EV2_CTRL | SCT event control register 2 |
EV3_STATE | SCT event state register 3 |
EV3_CTRL | SCT event control register 3 |
EV4_STATE | SCT event state register 4 |
EV4_CTRL | SCT event control register 4 |
EV5_STATE | SCT event state register 5 |
EV5_CTRL | SCT event control register 5 |
EVEN | SCT event enable register |
EVFLAG | SCT event flag register |
HALT | SCT halt condition register |
INPUT | SCT input register |
LIMIT | SCT limit register |
MATCH | SCT match value register of match channels 0 to 4; REGMOD0 to REGMODE4 = 0 |
MATCHREL | SCT match reload value register 0 to 4 REGMOD0 = 0 to REGMODE4 = 0 |
OUT0_SET | SCT output 0 set register |
OUT0_CLR | SCT output 0 clear register |
OUT1_SET | SCT output 1 set register |
OUT1_CLR | SCT output 1 clear register |
OUT2_SET | SCT output 2 set register |
OUT2_CLR | SCT output 2 clear register |
OUT3_SET | SCT output 3 set register |
OUT3_CLR | SCT output 3 clear register |
OUTPUT | SCT output register |
OUTPUTDIRCTRL | SCT output counter direction control register |
REGMODE | SCT match/capture registers mode register |
RES | SCT conflict resolution register |
RegisterBlock | Register block |
START | SCT start condition register |
STATE | SCT state register |
STOP | SCT stop condition register |