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#[doc = "Reader of register PORT_POL[%s]"] pub type R = crate::R<u32, super::PORT_POL>; #[doc = "Writer for register PORT_POL[%s]"] pub type W = crate::W<u32, super::PORT_POL>; #[doc = "Register PORT_POL[%s] `reset()`'s with value 0xffff_ffff"] impl crate::ResetValue for super::PORT_POL { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0xffff_ffff } } #[doc = "Reader of field `POL`"] pub type POL_R = crate::R<u32, u32>; #[doc = "Write proxy for field `POL`"] pub struct POL_W<'a> { w: &'a mut W, } impl<'a> POL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u32) -> &'a mut W { self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); self.w } } impl R { #[doc = "Bits 0:31 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."] #[inline(always)] pub fn pol(&self) -> POL_R { POL_R::new((self.bits & 0xffff_ffff) as u32) } } impl W { #[doc = "Bits 0:31 - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt."] #[inline(always)] pub fn pol(&mut self) -> POL_W { POL_W { w: self } } }